Loading...
Search for:
high-speed-arithmetic
0.008 seconds
CNTFET full-adders for energy-efficient arithmetic applications
, Article 6th International Conference on Computing, Communications and Networking Technologies, 13 July 2015 through 15 July 2015 ; 2015 ; 9781479979844 (ISBN) ; Hashemi, M ; Haghshenas, K ; Rezaee, S ; Rapolu, S ; Nikoubin, T ; University of North Texas ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
Abstract
In this paper, we present two energy-efficient full adders (FAs) which are a crucial building block of nano arithmetic logic units (nano-ALUs) with the Cell Design Methodology (CDM). Since the most suitable design configuration for CNT-based ICs is pass transistor configuration (PTL), CDM which properly benefits from PTL advantages is utilized. So the designs herewith take full advantages of simplicity, fewer transistors and better immunity against threshold voltage fluctuations of the PTL than the CCMOS configuration. CDM also resolves two problems of PTL by employing elegant mechanisms which are threshold voltage drop and loss of gain. Using the amend mechanisms and SEA sizing algorithm...