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Circuit-aging modeling based on dynamic MOSFET degradation and its verification
, Article International Conference on Simulation of Semiconductor Processes and Devices, SISPAD, 7 September 2017 through 9 September 2017 ; Volume 2017-September , 2017 , Pages 97-100 ; 9784863486102 (ISBN) ; Miyamoto, H ; Kikuchihara, H ; Navarro, D ; Maiti, T. K ; Ma, C ; Miura Mattausch, M ; Miremadi, S. G ; Mattausch, H. J ; Sharif University of Technology
Abstract
The reported investigation aims at developing a compact model for circuit-aging simulation. The model considers dynamic trap-density increase during circuit operation in a consistent way. The model has been applied to an SRAM cell, where it is believed that the NBTI effect dominates. Our simulation verifies that the hot-carrier effect has a compensating influence on the NBTI aging of SRAM cells. © 2017 The Japan Society of Applied Physics
LAXY: a location-based aging-resilient Xy-Yx routing algorithm for network on chip
, Article IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ; Volume 36, Issue 10 , 2017 , Pages 1725-1738 ; 02780070 (ISSN) ; Shirmohammadi, Z ; Zare, M ; Miremadi, S. G ; Sharif University of Technology
Abstract
Network on chip (NoC) is a scalable interconnection architecture for ever increasing communication demand between processing cores. However, in nanoscale technology size, NoC lifetime is limited due to aging processes of negative bias temperature instability, hot carrier injection, and electromigration. Usually, because of unbalanced utilization of NoC resources, some parts of the network experience more thermal stress and duty cycle in comparison with other parts, which may accelerate chip failure. To slow down the aging rate of NoC, this paper proposes an oblivious routing algorithm called location-based aging-resilient Xy-Yx (LAXY) to distribute packet flow over entire network. LAXY is...
Reliability Improvement in Aging-sensitive Units of a Processor
, Ph.D. Dissertation Sharif University of Technology ; Miremadi, Ghasem (Supervisor) ; Ejlali, Alireza (Supervisor)
Abstract
Despite the advantages of shrinking transistors’ dimensions, e.g. decrease in power consumption and fabrication cost and increase in their switching speed, it has an adverse impact on some characteristics of nano-scale (less than 130nm) transistors that can reduce the system lifetime. Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) are amongst the most important adverse effects of transistor shrinkage. These two effects, are known as transistor aging, decrease the switching speed of the transistors by increasing the threshold voltage and decreasing the charge carriers’ mobility in the channel of transistors. Temperature, operating voltage, and the size of transistors have...
Modeling of dynamic trap density increase for aging simulation of any MOSFET circuits
, Article European Solid-State Device Research Conference, 11 September 2017 through 14 September 2017 ; 2017 , Pages 192-195 ; 19308876 (ISSN) ; 9781509059782 (ISBN) ; Miyamoto, H ; Kikuchihara, H ; Navarro, D ; Maiti, T. K ; Rohbani, N ; Ma, C ; Mattausch, H. J ; Schiffmann, A ; Steinmair, A ; Seebacher, E ; Sharif University of Technology
Abstract
A compact aging model for circuit simulation has been developed by considering all possible trapped carriers within MOSFETs. The hot carrier effect and the N(P)BTI effect are modeled by integrating the substrate current as well as the oxide field change due to the trapped carriers. Additionally, the carriers trapped within the highly resistive drift region are included for high-voltage (HV)-MOSFET modeling. The aging model considers the dynamic trap-density increase as a function of circuit-operation time with dynamically varying stress conditions for each individual MOSFET. A self-consistent solution is obtained by iteratively solving the Poisson equation including the trap density. The...
Compact modeling of dynamic trap density evolution for predicting circuit-performance aging
, Article Microelectronics Reliability ; Volume 80 , 2018 , Pages 164-175 ; 00262714 (ISSN) ; Miyamoto, H ; Kikuchihara, H ; Maiti, T. K ; Rohbani, N ; Navarro, D ; Mattausch, H. J ; Sharif University of Technology
Abstract
It is shown that a compact MOSFET-aging model for circuit simulation is possible by considering the dynamic trap-density increase, which is induced during circuit operation. The dynamic trap/detrap phenomenon, which influences the switching performance, is also considered on the basis of well-known previous results. Stress-dependent hot-carrier effect and NBTI effect, origins of the device aging, are modeled during the circuit simulation for each device by integrating the substrate current as well as by determining the oxide-field change due to the trapped carriers over the individual stress-duration periods. A self-consistent solution can be obtained only by iteratively solving the Poisson...
Estimating and mitigating aging effects in routing network of FPGAs
, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 27, Issue 3 , 2019 , Pages 651-664 ; 10638210 (ISSN) ; Omidi, B ; Amrouch, H ; Henkel, J ; Asadi, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
In this paper, we present a comprehensive analysis of the impact of aging on the interconnection network of field-programmable gate arrays (FPGAs) and propose novel approaches to mitigate the aging effects on the routing network. We first show the insignificant impact of aging on data integrity of FPGAs, i.e., static noise margin and soft error rate of the configuration cells, as well as we show the negligible impact of the mentioned degradations on the FPGA performance. As such, we focus on the performance degradation of datapath transistors. In this regard, we propose a routing accompanied by a placement algorithm that prevents constant stress on transistors by evenly distributing the...