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    An 8-bit 160 MS/s folding-interpolating adc with optimizied active averaging/interpolating network

    , Article IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, 23 May 2005 through 26 May 2005 ; 2005 , Pages 6150-6153 ; 02714310 (ISSN) Azin, M ; Movahedian, H ; Bakhtiar, M. S ; Sharif University of Technology
    An 8-bit CMOS folding-interpolating analog-todigital converter is presented. A new method for designing optimized averaging circuit is also described. Careful circuit design and layout leads to a high-speed (160 MSPS) and low power (70 mW in 2.5 V supply voltage) ADC. The ADC is successfully implemented in 0.25um CMOS digital process and it takes 1x1.4 mm2 silicon area. © 2005 IEEE  

    Optimum supply and threshold voltages and transistor sizing effects on low power SOI circuit design

    , Article APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 4 December 2006 through 6 December 2006 ; 2006 , Pages 1394-1398 ; 1424403871 (ISBN); 9781424403875 (ISBN) Emadi, M ; Jafargholi, A ; Sargazi Moghadam, H ; Nayebi, M. M ; Sharif University of Technology
    In this work we introduce new model for energy-delay product and the performance of 80-nm SOI-CMOS circuits for the range of Vdd=0.1-1.5V and Vth=0-0.8V, are analyzed to find optimal Vdd and Vth BSIMSOI3.3 model (level 57) is used to verify the answers. We show that Energy-Delay Product (EDP) isn't appropriate metric for gate sizing problem. And a new design metric is introduced as a generalization of EDP. This metric is used to determine the transistor sizing for complex circuits based on the specified delay and energy constrains. In this case, unlike the conventional energy delay product metric, delay and energy can be considered with different emphasis. The complete design flowcharts and... 

    A novel genetic algorithm based method for efficient QCA circuit design

    , Article Advances in Intelligent and Soft Computing, 25 May 2012 through 27 May 2012, New Delhi ; Volume 166 AISC, Issue VOL. 1 , 2012 , Pages 433-442 ; 18675662 (ISSN) ; 9783642301568 (ISBN) Kamrani, M ; Khademolhosseini, H ; Roohi, A ; Sharif University of Technology
    In this paper we have proposed an efficient method based on Genetic Algorithms (GAs) to design quantum cellular automata (QCA) circuits with minimum possible number of gates. The basic gates used to design these circuits are 2-input and 3-input NAND gates in addition to inverter gate. Due to use of these two types of NAND gates and their contradictory effects, a new fitness function has been defined. In addition, in this method we have used a type of mutation operator that can significantly help the GA to avoid local optima. The results show that the proposed approach is very efficient in deriving NAND based QCA designs  

    Single event upset immune latch circuit design using C-element

    , Article Proceedings of International Conference on ASIC, 25 October 2011 through 28 October 2011, Xiamen ; 2011 , Pages 252-255 ; 21627541 (ISSN) ; 9781612841908 (ISBN) Rajaei, R ; Tabandeh, M ; Sharif University of Technology
    Downscaling trend in CMOS technology on the one hand and reducing supply voltage of the circuits on the other hand, make devices more susceptive to soft errors such as SEU. Latch circuits are prone to be affected by SEUs. In this article, we propose a new circuit design of latch using redundancy with the aim of immunity against SEUs. According to simulation results, our design not only guaranties full immunity, but also has the advantage of occupying less area and consuming much less power and performance penalty in comparison with other SEU immune latches. The simulation results show that our solution has 65.76% reduction in power and about 50.65% reduction in propagation delay in... 

    DsReliM: Power-constrained reliability management in Dark-Silicon many-core chips under process variations

    , Article International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2015, 4 October 2015 through 9 October 2015 ; Oct , 2015 , Pages 75-82 ; 9781467383219 (ISBN) Salehi, M ; Shafique, M ; Kriebel, F ; Rehman, S ; Tavana, M. K ; Ejlali, A ; Henkel, J ; ACM; IEEE ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Due to the tight power envelope, in the future technology nodes it is envisaged that not all cores in a many-core chip can be simultaneously powered-on (at full performance level). The power-gated cores are referred to as Dark Silicon. At the same time, growing reliability issues due to process variations and soft errors challenge the cost-effective deployment of future technology nodes. This paper presents a reliability management system for Dark Silicon chips (dsReliM) that optimizes for reliability of on-chip systems while jointly accounting for soft errors, process variations and the thermal design power (TDP) constraint. Towards the TDP-constrained reliability optimization, dsReliM... 

    Circuit design to improve security of telecommunication devices

    , Article 2017 IEEE 7th Annual Computing and Communication Workshop and Conference, CCWC 2017, 9 January 2017 through 11 January 2017 ; 2017 ; ISBN: 978-150904228-9 Bahrami, H ; Hajsadeghi, K ; Sharif University of Technology
    Security in mobile handsets of telecommunication standards such as GSM, Project 25 and TETRA is very important, especially when governments and military forces use handsets and telecommunication devices. Although telecommunication could be quite secure by using encryption, coding, tunneling and exclusive channel, attackers create new ways to bypass them without the knowledge of the legitimate user. In this paper we introduce a new, simple and economical circuit to warn the user in cases where the message is not encrypted because of manipulation by attackers or accidental damage. This circuit not only consumes very low power but also is created to sustain telecommunication devices in aspect... 

    A low-waste reliable adiabatic platform

    , Article Computers and Electrical Engineering ; Volume 89 , 2021 ; 00457906 (ISSN) Narimani, R ; Safaei, B ; Ejlali, A ; Sharif University of Technology
    Elsevier Ltd  2021
    Given the importance of reducing energy consumption and the challenge of heat generation in classic CMOS circuits, adiabatic circuits are believed as an appropriate alternative. Most of the adiabatic circuit families come with a dual-rail structure, which provides them with an inherent hardware redundancy. Although this redundancy could be used for improving their reliability, no studies have been previously conducted to exploit this feature. In this regard, in this paper, we show that by exploiting the inherent hardware redundancy in adiabatic circuits, their reliability could be improved, while imposing a relatively low amount of energy overhead. Subsequently, with utilizing the outcome... 

    A DLL-based frequency synthesizer for VHF DVB-H/T receivers

    , Article 2010 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, SM2ACD 2010, 4 October 2010 through 6 October 2010 ; October , 2010 ; 9781424468164 (ISBN) Gholami, M ; Sharifkhani, M ; Saeedi, S ; Atarodi, M ; Sharif University of Technology
    This paper presents a new architecture for a DLL based frequency synthesizer for wireless transceivers. Owing to its DLL based nature, the synthesizer generates the target frequencies with minimum phase noise. The proposed architecture takes the advantage of a combination of a frequency divider and an edge combiner to create the desired frequencies. As an example, the synthesizer is adopted to create the channel frequencies of French DVB-H/T standard. The circuit level design guidelines and power consumption trade-offs are presented. It was shown that for the mentioned standard a mere 6 stage delay line is sufficient. Simulation results confirm the analytical predictions  

    Systematic modeling and simulation of DLL-based frequency multiplier

    , Article 2010 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, SM2ACD 2010, 4 October 2010 through 6 October 2010 ; 2010 ; 9781424468164 (ISBN) Gholami, M ; Sharifkhani, M ; Ebrahimi, A ; Saeedi, S ; Atarodi, M ; Sharif University of Technology
    This paper represents a systematic procedure of simulating charge pump based delay locked loops (DLLs). The presented procedure is based on the systematic modelling of the DLL components in Matlab simulink simulator. The system has been designed for 1Hz input clock signal that by changing the whole system scale, it can be used for every other input frequencies. The simulation results in Matlab and design considerations for DLL based frequency multiplier are presented  

    Compact, low-voltage, low-power and high-bandwidth CMOS four-quadrant analog multiplier

    , Article 2010 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design, SM2ACD 2010, 4 October 2010 through 6 October 2010, Gammarth ; 2010 ; 9781424468164 (ISBN) Ebrahimi, A ; Miar Naimi, H ; Gholami, M ; Sharif University of Technology
    In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18μm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25μw quiescent power with 2GHz bandwidth and 1.5% THD  

    Reliability-aware design to suppress aging

    , Article 53rd Annual ACM IEEE Design Automation Conference, DAC 2016, 5 June 2016 through 9 June 2016 ; Volume 05-09 , June-2016 , 2016 ; 0738100X (ISSN); 9781450342360 (ISBN) Amrouch, H ; Khaleghi, B ; Gerstlauerz, A ; Henkel, J ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2016
    Due to aging, circuit reliability has become extraordinary challenging. Reliability-aware circuit design flows do virtually not exist and even research is in its infancy. In this paper, we propose to bring aging awareness to EDA tool flows based on so-called degradation-aware cell libraries. These libraries include detailed delay information of gates/cells under the impact that aging has on both threshold voltage (Vth) and carrier mobility (μ) of transistors. This is unlike state of the art which considers Vth only. We show how ignoring μ degradation leads to underestimating guard-bands by 19% on average. Our investigation revealed that the impact of aging is strongly dependent on the... 

    An efficient uniform-segmented neuron model for large-scale neuromorphic circuit design: Simulation and FPGA synthesis results

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 66, Issue 6 , 2019 , Pages 2336-2349 ; 15498328 (ISSN) Jokar, E ; Abolfathi, H ; Ahmadi, A ; Ahmadi, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Large-scale simulation of spiking neural networks on hardware with a remarkable resemblance to their mathematical models is a key objective of the neuromorphic discipline. This issue is, however, considerably resource-intensive due to the presence of nonlinear terms in neuron models. This paper proposes a novel uniform piecewise linear segmentation approach for nonlinear function evaluations. Employing the proposed approach, we present a uniform-segmented adaptive exponential neuron model capable of accurately producing various responses exhibited by the original model and suitable for efficient large-scale implementation. In contrast to previous nonuniform-segmented neuron models, the... 

    Wireless optical CDMA LAN: digital design concepts

    , Article IEEE Transactions on Communications ; Volume 56, Issue 12 , 2008 , Pages 2145-2155 ; 00906778 (ISSN) Ghaffari, B. M ; Matinfar, M. D ; Salehi, J. A ; Sharif University of Technology
    In this paper we study and present an in-depth analysis on the operability and the viability of a typical wireless optical CDMA (OCDMA) local area network. Three receiver structures for OCDMA systems, using optical orthogonal codes (OOC) with minimum auto and cross-correlations as signature sequence, namely, correlation, correlation with hard-limiter, and chip-level detection are studied and proposed for such a network. For the synchronization circuit design the performance of two algorithms for OOC based OCDMA networks, namely, simple serial-search and multiple-shift in the context of wireless OCDMA LAN are studied. Furthermore, we study a synchronization method based on matched filtering... 

    A new low voltage, high PSRR, CMOS bandgap voltage reference

    , Article 2008 IEEE International SOC Conference, SOCC, Newport Beach, CA, 17 September 2008 through 20 September 2008 ; 2008 , Pages 345-348 ; 9781424425969 (ISBN) Ashrafi, S. F ; Atarodi, M ; Chahardori, M ; Sharif University of Technology
    A new low voltage bandgap reference (BGR) in CMOS technology, with high power supply rejection ratio (PSRR) is presented. The proposed circuit uses a regulated current mode structure and some feedback loops to reach a low voltage, low power and high PSRR voltage reference. The circuit was designed and simulated in 0.18um CMOS technology, with a power supply of 1.4 volt. The results show PSRR is 65dB at 1MHz and the output voltage variation versus temperature (-40 to 140) is less than 0.1%. This circuit shows robustness against process variation. ©2008 IEEE  

    Investigating the Baldwin effect on Cartesian Genetic Programming efficiency

    , Article 2008 IEEE Congress on Evolutionary Computation, CEC 2008, Hong Kong, 1 June 2008 through 6 June 2008 ; 2008 , Pages 2360-2364 ; 9781424418237 (ISBN) Khatir, M ; Jahangir, A. H ; Beigy, H ; Sharif University of Technology
    Cartesian Genetic Programming (CGP) has an unusual genotype representation which makes it more efficient than Genetic programming (GP) in digital circuit design problem. However, to the best of our knowledge, all methods used in evolutionary design of digital circuits deal with rugged, complex search space, which results in long running time to obtain successful evolution. Therefore, employing a method to guide evolution in these spaces can facilitate achieving more reasonable results. It has been claimed that a two-step evolutionary scenario caused by benefit and cost of learning called Baldwin effect can guide evolution in the biology and artificial life. Therefore, we have been motivated...