Sharif Digital Repository

Solid State Drives (SSDs) have recently emerged as a high speed random access alternative to classical magnetic disks. To date, SSD designs have been largely based on multi-channel bus architecture that confronts serious scalability problems in high-end enterprise SSDs with dozens of flash memory chips and a gigabyte host interface. This forces the community to rapidly change the bus-based inter-flash standards to respond to ever increasing application demands. In this paper, we first give a deep look at how different flash parameters and SSD internal designs affect the actual performance and scalability of the conventional architecture. Our experiments show that SSD performance improvement... 

Performance of a data center is a function of three features; bandwidth, latency, and reliability. By adopting optical technology in data center network, bandwidth increment, in addition to reduction of transmission latency and power consumption, is achieved. Unfortunately, fault tolerance of the optical networks has raised less attention so far. So in this paper, we propose a fault-tolerant, scalable, and high-performance optical architecture built upon previously proposed O-TF network, with the goal of redundancy optimization and reducing the minimum number of wavelength channels required for non-blocking functionality of the network. Moreover, reducing network diameter, in O-FTF network... 

Data center performance is affected by three main factors; bandwidth, latency, and reliability of intra-data center interconnection network. Bandwidth and latency are definitely improved by adopting optical technology for intra-data center communication, but fault tolerance of the corresponding optical networks has been raised less. Recently, we introduced two Torus-based, all-optical, and non-blocking networks, i.e. O-TF and O-FTF, addressing reliability of optical networks, and now, in this paper, to address the scalability problem, we propose a novel Optical Clos-based architecture which reduces minimum number of required wavelength channels, as well as, the switch size in each node.... 

Exponential growth of traffic and bandwidth demands in current data center networks requires low-latency high-throughput interconnection networks, considering power consumption. By considering growth of both multicast and unicast applications, power efficient communication becomes one of the main design challenges in today's data center networks. Addressing these demands, optical networks suggest several benefits as well as circumventing most disadvantages of electrical networks. In this paper, we propose an all-optical scalable architecture, named as OMUX, for communicating intra-data centers. This architecture utilizes passive optical devices and enables optical circuit switching without... 

The surface area which is defined as the number of vertices at a given distance from a base vertex of a graph is considered to be as one of the most useful yet abstract combinatorial properties of a graph. The applicability of surface area spans many problem spaces such as those in parallel and distributed computing. These problems normally involve combinatorial analysis of underlying graph structures (e.g., spanning tree construction, minimum broadcast algorithms, efficient VLSI layout, performance modeling). In this paper, we focus on the problem of finding the surface area of a class of popular graphs, namely the family of WK-recursive and swapped networks. These are attractive networks... 

On-chip interconnections play an important role in multi/many-processor systems-on-chip (MPSoCs). In order to achieve efficient optimization, each specific application must utilize a specific architecture, and consequently a specific interconnection network. For design space exploration and finding the best NoC solution for each specific application, a fast and flexible NoC simulator is necessary, especially for large design spaces. In this paper, we present an FPGA-based NoC co-simulator, which is able to be configured via software. In our proposed NoC simulator, entitled DuCNoC, we implement a Dual-Clock router micro-architecture, which demonstrates 75x-350x speed-up against BOOKSIM.... 

Optical networks-on-chip are introduced as an alternative for electrical interconnects in many-core systems, due to their low delay and power consumptions, as well as their high bandwidths. Despite these advantages, physical characteristics of the photonic components are highly sensitive to thermal variations, which results in optical data misrouting through the optical networks at the presence of temperature fluctuation. In this paper, we propose a thermally-resilient all-optical communication approach which improves reliability, as well as performance of the optical networks. For this purpose, we take advantages of auxiliary waveguides and a novel wavelength assignment approach to avoid... 

In this paper, we present a comprehensive analysis of the impact of aging on the interconnection network of field-programmable gate arrays (FPGAs) and propose novel approaches to mitigate the aging effects on the routing network. We first show the insignificant impact of aging on data integrity of FPGAs, i.e., static noise margin and soft error rate of the configuration cells, as well as we show the negligible impact of the mentioned degradations on the FPGA performance. As such, we focus on the performance degradation of datapath transistors. In this regard, we propose a routing accompanied by a placement algorithm that prevents constant stress on transistors by evenly distributing the...