Sharif Digital Repository

In this paper, we argue that communication at the speed of light (CaSoL) through on-chip copper interconnects is possible in the near future based on giga-scale integration (GSI) technologies. A three-step algorithm is introduced to design the optimum buffers in such systems. HSPICE simulations show that a 1.3× time of flight (TF) is reachable in 7-nm FinFET technology. It is also shown that such a design is by nature, robust, and immune to process variations and crosstalk noise. © 1963-2012 IEEE  

In this study, the performance of virtual cut-through switching in the cube-based OTIS architecture, an optoelectronic interconnection architecture for multicomputer systems, is empirically analyzed. Deadlock-free deterministic and adaptive minimal path routing algorithms for this architecture are introduced, and the effects of different network and traffic parameters on average message latency are investigated. This analysis presents a relatively more realistic view of the OTIS architecture than that presented in previous work by considering issues related to a lower level of abstraction (the routing and switching of messages). Among other results, the analysis indicates that depending on... 

Cryogenic technologies not only improve the performance of interconnects but also the performance of transistors and consequently drivers and repeaters. Although in cryogenically cooled integrated circuits the local temperature of interconnects and transistors may be as low as 50 K, it may easily reach to 600 K in high-temperature chips. In this brief, we investigated the impact of temperature on the delay of local, intermediate, unit-repeater-inserted (URI), and cascaded repeater-inserted (CRI) global copper interconnects for minimum technology node with available transistor model (32-nm technology). Our results show that temperature variation of driver resistance could change the delay of... 

Time domain analysis of multilayer graphene nano ribbon (MLGNR) interconnects, based on transmission line modeling (TLM) using a six-order linear parametric expression, has been presented for the first time. We have studied the effects of interconnect geometry along with its contact resistance on its step response and Nyquist stability. It is shown that by increasing interconnects dimensions their propagation delays are increased and accordingly the system becomes relatively more stable. In addition, we have compared time responses and Nyquist stabilities of MLGNR and SWCNT bundle interconnects, with the same external dimensions. The results show that under the same conditions, the... 

As a result of the emerging use of mesh-based multicomputers (and recently mesh-based multiprocessor systems-on-chip), issues related to processor management have attracted much attention. In a mesh-based multiprocessor, after repeated submesh allocations and de-allocations, the system network may be fragmented, i.e. there might be unallocated nodes in the network. As a result, in a system with contiguous processor allocation, no new tasks can start running due to the lack of enough free adjacent processors to form a suitable submesh. Although there might be enough free processors available, they remain idle until the allocator can find a set of adjacent free nodes forming a submesh to be... 

The performance of gigascale integration chips improves by cryogenic technologies such as subambient cooling. In these conditions, interconnects may perform at temperatures as low as 50 K. However, the local temperature of interconnects could easily be as high as 600 K at high-temperature chips. In this brief, we investigated the impact of temperature on delay of local, intermediate, and global interconnects of International Technology Roadmap for Semiconductors Node 2024. This is done for different values of interconnect width and length, nanotube diameter, and percentage of metallic carbon nanotubes (CNTs) in a grown bundle. Results are compared with those of copper counterpart. We showed... 

In this paper, we propose a solution for the problem of capturing an intruder in two popular interconnection topologies namely, the mesh and the torus. A set of agents collaborate to capture a hostile intruder in the network. While the agents can move in the network one hop at a time, the intruder is assumed to be arbitrarily fast i.e. it can traverse any number of nodes contiguously as far as there are no agents in those nodes. Here we consider a new version of the problem where each agent can replicate new agents when needed, i.e. the algorithm starts with a single agent and new agents are created on demand. We define a new class of algorithms for capturing an intruder. In particular, we... 

The cellular learning automata, which is a combination of cellular automata, and learning automata, is a new recently introduced model. This model is superior to cellular automata because of its ability to learn and is also superior to a single learning automaton because it is a collection of learning automata which can interact with each other. The basic idea of cellular learning automata, which is a subclass of stochastic cellular learning automata, is to use the learning automata to adjust the state transition probability of stochastic cellular automata. In this paper, we first provide a mathematical framework for cellular learning automata and then study its convergence behavior. It is... 

Although several analytical models have been proposed in the literature for binary n-cubes with deterministic routing, most of them have not included the effects of virtual channel multiplexing on network performance. The only mathematical model for deterministic wormhole routing in hypercubes with virtual channels was proposed in [Y. Boura, Design and Analysis of Routing Schemes and Routers for Wormhole-routed Mesh Architectures, Ph.D. Thesis, Department of Computer Science and Engineering, Pennsylvania State University, 1995] which uses complex combinatorial analysis with a computation time of O(N = 2n) for an n-dimensional hypercube. This paper proposes a new and simple analytical model... 

This paper introduces a parallel algorithm for computing an N = n2n point Lagrange interpolation on an n-dimensional cube-connected cycles (CCCn). The algorithm consists of three phases: initialisation, main and final. While there is no computation in the initialisation phase, the main phase is composed of n2n-1 steps, each consisting of four multiplications, four subtractions and one communication operation, and an additional step including one division and one multiplication. The final phase is carried out in two sub-phases. There are [n/2] steps in the first sub-phase, each including two additions and one communication, followed by the second sub-phase which comprises n steps each... 

In optoelectronic OTIS multicomputer networks (also known as Swapped networks), electrical and optical interconnects are used for local and global communication, respectively. An interesting instance of the OTIS multicomputers is the OTIS-mesh. Pancyclicity is of great importance in the implementation of a variety of parallel algorithms in multicomputers. This paper addresses the Pancyclicity problem of OTIS-mesh. More precisely, we prove that if the factor graph G of an OTIS network is a 2-D or 3-D mesh with at least one even radix, OTIS-G can embed any cycle of length l, l?{4,6,7,8,9,...,|G|2}  

Multilevel interconnect network of a macrocell for 7.5 nm technology node is designed with carbon based interconnects (CBI) and Cu. Results are compared. Constrains of using CBI is discussed. It is shown that by using CBI power dissipation associated with wires could decrease by 32%. To use GNRs for more than one metal pair, reverse wire pitch idea is proposed that prevents undesirable increase in the number of metal layers  

In optoelectronic OTIS multicomputer networks (also known as Swapped networks), electrical and optical interconnects are used for local and global communication, respectively. An interesting instance of the OTIS multicomputers is the OTIS-mesh. Pancyclicity is of great importance in the implementation of a variety of parallel algorithms in multicomputers. This paper addresses the Pancyclicity problem of OTIS-mesh. More precisely, we prove that if the factor graph G of an OTIS network is a 2-D or 3-D mesh with at least one even radix, OTIS-G can embed any cycle of length l, l∈{4,6,7,8,9,...,|G|2}  

Pipelined on-chip interconnects are used in on-chip networks to increase the throughput of interconnects and to achieve freedom in choosing arbitrary network topologies. Since reliability and energy consumption are prominent issues in on-chip networks, they should be carefully considered in the design of pipelined interconnects. In this paper, ws propose the use of energy recovery techniques to construct low energy and reliable pipelined on-chip interconnects. The proposed designs have been evaluated using detailed SPICE simulations. In the reliability analysis, the SEU fault model is considered as it is a major reliability concern in the sequential circuits (pipelining memory elements)... 

The star graph was introduced as an attractive alternative to the well-known hypercube and its properties have been well studied in the past. Most of these studies have focused on topological properties and algorithmic aspects of this network. Although several analytical models have been proposed in the literature for different interconnection networks, none of them have dealt with star graphs. This paper proposes the first analytical model to predict message latency in wormhole-switched star interconnection networks with fully adaptive routing. The analysis focuses on a fully adaptive routing algorithm which has shown to be the most effective for star graphs. The results obtained from... 

In this paper, n-tier methodology is developed to design multilevel interconnect architecture of macrocells using single-wall carbon nanotube (SWCNT) bundles. Upper limit of low-bias voltage of SWCNT bundle interconnects is derived and its dependence on temperature, SWCNTs' diameter, and interconnect length is studied. Possibility of using SWCNT bundles as local interconnects at 7.5-nm technology node is discussed, and it is shown that SWCNT bundles with 1 nm diameter cannot be used at the first interconnect metal level. Using Cu and SWCNT bundles, multilevel interconnect architecture of a 7.5-nm ASIC macrocell is designed which reduces the number of metal levels by 27% and power dissipation... 

On-chip interconnections play an important role in multi/many-processor systems-on-chip (MPSoCs). In order to achieve efficient optimization, each specific application must utilize a specific architecture, and consequently a specific interconnection network. For design space exploration and finding the best NoC solution for each specific application, a fast and flexible NoC simulator is necessary, especially for large design spaces. In this paper, we present an FPGA-based NoC co-simulator, which is able to be configured via software. In our proposed NoC simulator, entitled DuCNoC, we implement a Dual-Clock router micro-architecture, which demonstrates 75x-350x speed-up against BOOKSIM.... 

Optical networks-on-chip are introduced as an alternative for electrical interconnects in many-core systems, due to their low delay and power consumptions, as well as their high bandwidths. Despite these advantages, physical characteristics of the photonic components are highly sensitive to thermal variations, which results in optical data misrouting through the optical networks at the presence of temperature fluctuation. In this paper, we propose a thermally-resilient all-optical communication approach which improves reliability, as well as performance of the optical networks. For this purpose, we take advantages of auxiliary waveguides and a novel wavelength assignment approach to avoid... 

Solid State Drives (SSDs) have recently emerged as a high speed random access alternative to classical magnetic disks. To date, SSD designs have been largely based on multi-channel bus architecture that confronts serious scalability problems in high-end enterprise SSDs with dozens of flash memory chips and a gigabyte host interface. This forces the community to rapidly change the bus-based inter-flash standards to respond to ever increasing application demands. In this paper, we first give a deep look at how different flash parameters and SSD internal designs affect the actual performance and scalability of the conventional architecture. Our experiments show that SSD performance improvement... 

Performance of a data center is a function of three features; bandwidth, latency, and reliability. By adopting optical technology in data center network, bandwidth increment, in addition to reduction of transmission latency and power consumption, is achieved. Unfortunately, fault tolerance of the optical networks has raised less attention so far. So in this paper, we propose a fault-tolerant, scalable, and high-performance optical architecture built upon previously proposed O-TF network, with the goal of redundancy optimization and reducing the minimum number of wavelength channels required for non-blocking functionality of the network. Moreover, reducing network diameter, in O-FTF network...