Loading...
Search for:
interleaved-converters
0.008 seconds
Compensation and Calibration of ADCs
, M.Sc. Thesis Sharif University of Technology ; Sharif Khani, Mohammad (Supervisor)
Abstract
Increasing demand for high-speed and high-resolution ADCs as much as low-power ones and on the other hand, the obstacles in the way of reaching them make calibration and compensation methods more significant for obtaining ADCs with the better specs. Among the cases which need modification, the modification of C-2C-based SAR ADCs, which can decrease the power significantly, and the modification of time-skew error of time-interleaved ADCs, which is the main and the most challenging error in this type of ADCs, could be the two of the effective ways to making the State-of-the-Art ADCs. In this project for the first time, a novel compensation method for C-2C parasitic charges is proposed which...
Fast and simple open-circuit fault detection method for interleaved DC-DC converters
, Article 7th Power Electronics, Drive Systems and Technologies Conference, PEDSTC 2016, 16 February 2016 through 18 February 2016 ; 2016 , Pages 440-445 ; 9781509003754 (ISBN) ; Zolghadri, M. R ; Ouni, S ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2016
Abstract
Interleaved DC-DC boost converters are interesting choices in applications like fuel cells and photovoltaic systems. Although this converter offers low current ripple, but an open-circuit switch fault can lead to unacceptable current ripples. In this paper, a very fast and simple method is proposed to detect an open-circuit switch fault and its location. This method doesn't need any additional sensors, is efficient in CCM and DCM modes of operation, and can detect the fault in less than one switching period. Moreover, this method is suitable for implementation on an FPGA, due to the use of simple math and state machine blocks. Simulations are carried out to validate the effectiveness of this...
Family of interleaved high step-up DC-DC converters utilizing multi-winding coupled inductors
, Article 13th Power Electronics, Drive Systems, and Technologies Conference, PEDSTC 2022, 1 February 2022 through 3 February 2022 ; 2022 , Pages 555-560 ; 9781665420433 (ISBN) ; Tarzamni, H ; Sabahi, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2022
Abstract
This paper proposes a family of interleaved DC-DC converters for high step-up applications based on multi-winding coupled inductors, which utilize inductive and capacitive approaches to transfer the input energy to the output load. The wide output load voltage level of the proposed converter depends on the switches duty cycle and the coupled inductor (CI) turns ratio. As some features, interleaving and cascading help the converters achieve high output voltage gain, low input current ripple, low-volume input inductor, and high reliability. Moreover, employing multi-winding coupled inductors improves output voltage gain, recycles the magnetic components stored energy, cancels circulating...
10-Bit 500-MS/s Pipelined Analog to Digital Converter
, M.Sc. Thesis Sharif University of Technology ; Hajsadeghi, Khosrow (Supervisor)
Abstract
High speed data converters are very often used in telecommunication systems. Since these systems are increasingly used in mobile form reducing the power consumption in these circuits is of great importance. The goal of this project was to design a pipeline 10 bit converter for a sample rate of 500 M sample/s with a power consumption of 50mW for the input level of 1Vp-p and a 1.5V power supply in 0.18μm CMOS technology. To reach these goals a number of low-power techniques are proposed in various levels of abstraction. In system level, the sampling and feedback capacitors, as well as the stage resolution of the ADC is optimized .And to...
Design of a High Speed Time-Interleaved SAR ADC
, M.Sc. Thesis Sharif University of Technology ; Sharifkhani, Mohammad (Supervisor) ; Fotowat Ahmadi, Ali (Supervisor)
Abstract
The digital nature of Successive Approximation Register (SAR) Analog to Digital Converter (ADC) suits them for the new technologies with small gate length and low power applications. Applications such as ultra-wideband receivers, satellite receivers and high speed serial links demand medium resolution and high sampling rate ADCs. Due to binary search algorithm speed limitations, SAR ADCs belong to low to moderate speed category. In this thesis time-interleaving and two-bit-per-cycle technique are used in order to increase SAR ADC sampling rate. These techniques are both sensitive to offset and if the comparators used in SAR ADC have different offsets signal-to-noise-and-distortion will be...
A reliable and fast response buck converter based on interleaved converter
, Article 27th Iranian Conference on Electrical Engineering, ICEE 2019, 30 April 2019 through 2 May 2019 ; 2019 , Pages 804-807 ; 9781728115085 (ISBN) ; Kaboli, S ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
Power Distribution Unit (PDU) is a power supply unit that supplies various DC voltage levels for electric equipment. Reliability of PDU is very important in electrical systems. Buck converter is frequently used in PDU to provide the lower voltage levels than the source voltage level. The output capacitor of the buck converter is the main factor of failure. In this paper, we present a method to design a buck converter with almost no inductor current ripple. If the inductor current ripple is eliminated, the output capacitor can be removed from the converter. By removing the capacitor, the reliability and transient response of the converter can be improved considerably. The proposed method is...