Sharif Digital Repository

A Triangulated Irregular Network (TIN) is a data structure that is usually used for representing and storing monotone geographic surfaces, approximately. In this representation, the surface is approximated by a set of triangular faces whose projection on the XY-plane is a triangulation. The visibility graph of a TIN is a graph whose vertices correspond to the vertices of the TIN and there is an edge between two vertices if their corresponding vertices on TIN see each other, i.e. the segment that connects these vertices completely lies above the TIN. Computing the visibility graph of a TIN and its properties have been considered thoroughly in the literature. In this paper, we consider this... 

Networks on Chip1 have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties 2 which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores on to the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs on to the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs to be... 

Irregular networks provide more scalability and better cost-performance for network-based parallel computing systems. There has been much work done on developing routing algorithms for this class of networks. In this paper, a general methodology for generating deadlock-free routing algorithms for irregular networks is proposed. It not only introduces three novel efficient routing algorithms, but also covers the three best-known routing algorithms already proposed for irregular networks in the literature, namely Up/Down, Left/Right, and L-turn routing algorithms. As revealed by simulation results, the performance of the six routing algorithms mainly depends on network topology and different... 

Irregular topologies are desirable network structures for building scalable cluster systems and very recently they have also been employed in SoC (system-on-chip) design. Many analytical models have been proposed in the literature to evaluate the performance of networks with different topologies such as hypercube, torus, mesh, hypermesh, Cartesian product networks, star graph, and k-ary n-cube; however, to the best of our knowledge, no mathematical model has been presented for irregular networks. Therefore, as an effort to fill this gap, this paper presents a comprehensive mathematical model for fully adaptive routing in wormhole-switched irregular networks. Moreover, since our approach... 

Networks on chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties (IP) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores onto the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs onto the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs... 

In this paper, a diverse range of routing algorithms is classified into a new family of routings called zone-ordered label-based routing algorithms. The proposed classification is based on three common steps (factors) for generating such routings, namely, graph labeling, deadlock-free zones, and zone ordering. The main goal of this classification is to define several new routing concepts and streamline the knowledge on routing algorithms. Following the classification, a novel methodology is proposed to generate routing algorithms for irregular networks. The methodology uses the three mentioned steps to generate deadlock-free routings. Consequently, the methodology-based routings fall into... 

In this paper, a diverse range of routing algorithms is classified into a new family of routings called zone-ordered label-based routing algorithms. The proposed classification is based on three common steps (factors) for generating such routings, namely, graph labeling, deadlock-free zones, and zone ordering. The main goal of this classification is to define several new routing concepts and streamline the knowledge on routing algorithms. Following the classification, a novel methodology is proposed to generate routing algorithms for irregular networks. The methodology uses the three mentioned steps to generate deadlock-free routings. Consequently, the methodology-based routings fall into... 

This paper presents a general methodology for generating deadlock-free routing algorithms for irregular networks. Constructing a spanning tree on the given network, assigning directions to the network channels, creating deadlock-free zones, and specifying a logical sequence of the produced deadlock-free zones are the four fundamental steps that the proposed methodology takes to generate deadlock-free and connected routing algorithms. By applying the proposed methodology with two known labeling methods we have generated six irregular routing algorithms: three of them are novel routing algorithms and three of them (the Up/Down, Left/Right, and L-turn routing algorithms) have already been... 

Networks on chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties (IP) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores onto the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs onto the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs... 

So far, many analytical models have been proposed in the literature to evaluate the performance of networks with different topologies such as hypercube, torus, mesh, hypermesh, Cartesian product networks, star graph, and k-ary n-cube; however, to the best of our knowledge, no mathematical model has been presented for irregular networks. Therefore, as an effort to fill this gap, this paper presents a comprehensive mathematical model for fully adaptive routing in wormhole-switched irregular networks. Moreover, since our approach holds no assumption for the network topology, the proposed analytical model covers all the aforementioned models (i.e. it covers both regular and irregular... 

This paper presents a new serial algorithm for selecting a nearly minimum number of vertex-guards so that all parts of a geographical surface modeled by a TIN (Triangulated Irregular Networks) is covered. Our algorithm selects fewer guards than the best existing algorithms on the average. Based on this approach, a new coarse-grain parallel algorithm for this problem is proposed. It has been showed that the upper bound for total number of guards, selected by this algorithm, is where n is number of vertices in the TIN. Average case analysis and implementation results show that in real TINs even fewer than guards (proved upper bound of needed guards in worse-case) are selected by our serial and...