Sharif Digital Repository

The ever-expanding growth of internet traffic enforces deployment of massive Data Center Networks (DCNs) supporting high performance communications. Optical switching is being studied as a promising approach to fulfill the surging requirements of large scale data centers. The tree-based optical topology limits the scalability of the interconnected network due to the limitations in the port count of optical switches and the lack of optical buffers. Alternatively, buffer-less Fast Optical Switch (FOS) was proposed to realize the nanosecond switching of optical DCNs. Although FOSs provide nanosecond optical switching, they still suffer from port count limitations to scale the DCN. To address... 

This paper presents an energy-efficient communication protocol which distributes a uniform energy load to the sensors in a wireless microsensor network. This protocol, called Distance-Based Segmentation (DBS), is a clusterbased protocol that divides the entire network into equalarea segments and applies different clustering policies to each segment to reduce total energy dissipation and hence prolong the lifetime of the network. To evaluate the DBS protocol, a simulator was implemented using the MATLAB software. Simulation results show that the DBS can achieve as much as 16% reduction in total dissipated energy as compared with conventional protocols. In addition this protocol is able to... 

Elliptic curve cryptography (ECC) has received attention, because it can achieve the same security level as other asymmetric methods while using a key with smaller length. Although ECC is more efficient compared with other asymmetric methods, the fast computation of ECC is always desirable. In this paper, a fixed-base comb point multiplication method has been used to perform regular point multiplication. In addition, two low-complexity (LC) and low-latency (LL) architectures for the regular point multiplication using fixed-base comb method have been proposed. The point multiplication architectures have been implemented using field-programmable gate array and application-specific integrated... 

Chip multiprocessors (CMPs) require a low-latency interconnect fabric network-on-chip (NoC) to minimize processor stall time on instruction and data accesses that are serviced by the last-level cache (LLC). While packet-switched mesh interconnects sacrifice performance of many-core processors due to NoC-induced delays, existing circuit-switched interconnects do not offer lower network delays as they cannot hide the time it takes to set up a circuit. To address this problem, this work introduces CIMA - a hybrid circuit-switched and packet-switched mesh-based interconnection network that affords low LLC access delays at a small area cost. CIMA uses virtual cut-through (VCT) switching for short... 

Server workloads benefit from execution on many-core processors due to their massive request-level parallelism. A key characteristic of server workloads is the large instruction footprints. While a shared last-level cache (LLC) captures the footprints, it necessitates a low-latency network-on-chip (NOC) to minimize the core stall time on accesses serviced by the LLC. As strict quality-of-service requirements preclude the use of lean cores in server processors, we observe that even state-of-the-art single-cycle multi-hop NOCs are far from ideal because they impose significant NOC-induced delays on the LLC access latency, and diminish performance. Most of the NOC delay is due to per-hop... 

In this paper, a dynamic-hybrid automatic repeat request (D-HARQ) scheme with guaranteed delay performance is proposed. As opposed to the conventional HARQ that the maximum number of re-transmissions, L, is fixed, in the proposed scheme packets can be re-transmitted more times given that the previous packet was received with less than L re-transmissions. The dynamic of the proposed scheme is analyzed using the Markov model. For delay sensitive applications, the proposed scheme shows a superior performance in terms of packet error rate compared with the conventional HARQ and Fixed retransmission schemes when the channel state information is not available at the transmitter. We further show... 

Low-latency data access is crucial in edge clouds serving autonomous vehicles. Storage I/O caching is a promising solution to deliver the desired storage performance at a reasonable cost in vehicular edge platforms. Current storage I/O caching methods, however, are not specialized for workload characteristics and demands of autonomous vehicles and/or do not consider the communication latency between the vehicle and the base station hosting the edge cloud node. In this work, we propose a storage mechanism for vehicular edge cloud platforms taking communication, I/O cache, and storage latencies into account. We evaluate our proposed framework using realistic storage traces of vehicular... 

This paper presents a hybrid QR decomposition (QRD) design that reduces the number of computations and increases their execution parallelism by using a unique combination of Multi-dimensional Givens rotations, Householder transformations and conventional 2-D Givens rotations. A semi-pipelined semi-iterative architecture is presented for the QRD core, that uses innovative design ideas to develop 2-D, Householder 3-D and 4-D/2-D configurable CORDIC processors, such that they can perform the maximum possible number of vectoring and rotation operations within the given number of cycles, while minimizing gate count and maximizing the resource utilization. Test results for the 0.3 mm 2 QRD chip,... 

Ink drop spread (IDS) is the engine of an active learning method, which is the methodology of soft computing. IDS, as a pattern-based processing unit, extracts useful information from a system that is subjected to modeling. In spite of its excellent potential to solve problems such as classification and modeling compared with other soft-computing tools, finding its simple and fast hardware implementation is still a challenge. This paper describes a new hardware implementation of the IDS method that is based on the memristor crossbar structure. In addition to simplicity, being completely real time, having low latency, and the ability to continue working properly after the occurrence of power... 

In this paper, we propose a packet-switched network-on-chip (NoC) architecture which can provide a number of low-power, low-latency virtual point-to-point connections for communication flows. The work aims to improve the power and performance metrics of packet-switched NoC architectures and benefits from the power and resource utilization advantages of NoCs and superior communication performance of point-to-point dedicated links. The virtual point-to-point connections are set up by bypassing the entire router pipeline stages of the intermediate nodes. This work addresses constructing the virtual point-to-point connections at run-time using a light-weight setup network. It involves monitoring...