Search for: low-power
Total 212 records
An ultra low-power digital to analog converter for SAR ADCs, Article Proceedings of the International Conference on Microelectronics, ICM, 10 December 2017 through 13 December 2017 ; Volume 2017-December , 2018 , Pages 1-4 ; 9781538640494 (ISBN) ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2018
A new structure of Capacitive Digital to Analog Converters (CDAC) for SAR ADCs is presented. In this structure, a number of capacitors are used in different series configurations to generate desirable voltage levels based on an input binary code. the proposed CDAC consumes a certain amount of power regardless of the input code. This method achieves more than 99.9% power reduction and 98.9% area reduction compared to the conventional binary weighted CDAC. © 2017 IEEE
Optimum experimental condition in oxygen gas-assisted low power Nd:Yag laser cutting, Article Modern Physics Letters B ; Volume 23, Issue 6 , 2009 , Pages 877-890 ; 02179849 (ISSN) ; Golnabi, H ; Sharif University of Technology
The optimum condition for the reactive gas-assisted Nd:YAG laser cuttings is described in this article. The cut kerf width is investigated for a laser power range of 50-170 W and a gas pressure of 1-6 bar for steel and mild steel materials. Variation of sample thickness, material type, gas pressure and the laser power on the cut width and slot quality are considered in this study. An overall 338 experiments at different experimental conditions are performed and the kerf results are compared. Optimum conditions for the steel and mild steel materials with a thickness range of 1-2 mm are obtained. The optimum condition for the steel cutting results in a minimum kerf width of 0.2 mm at a laser...
An efficient fast switching procedure for stepwise capacitor chargers, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 25, Issue 2 , 2017 , Pages 705-713 ; 10638210 (ISSN) ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2017
A new low-power switching procedure for stepwise capacitor chargers is presented. In this procedure, a novel displacement method is utilized to improve the speed by a factor of two while preserving energy efficiency. Moreover, the load capacitor retains its charge after the charging process finishes and permits the circuit charge another predischarged load capacitor without an efficiency degradation problem (instability). Also, the control circuit of the switching procedure is implemented using only flip-flops with no combinational logic, therefore, it systematically prevents glitch power dissipation and improves the efficiency. Analytical derivations are proposed to model the switching...
An Ultra Low-power Low-offset Double-tail Comparator, Article 17th IEEE International New Circuits and Systems Conference, NEWCAS 2019, 23 June 2019 through 26 June 2019 ; 2019 ; 9781728110318 (ISBN) ; Saeidi, R ; Sharifkhani, M ; Taherinejad, N ; Cadence; FAB - Mixed-Signal Foundry Experts; Infineon ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2019
In double tail comparators, the pre-amplifier amplifies the input differential voltage and when the output Vcm of the pre-amplifier becomes larger than Vth of the latch input transistors, the latch is activated and finalizes the comparison. As a result, the pre-amplification delay is fixed to a value and cannot be set at the minimum required delay, to save power and improve offset. In fact, when the latch is activated the pre-amplifier output differential voltage is still growing but the latch finishes the comparison before the maximum differential gain is formed and applied to the latch. In this paper, a comparator is proposed in which the preamplifier is turned off when the maximum gain is...
A combinational logic optimization for majority gate-based nanoelectronic circuits based on GA, Article 2011 International Semiconductor Device Research Symposium, ISDRS 2011, College Park, MD, 7 December 2011 through 9 December 2011 ; 2011 ; 9781457717550 (ISBN) ; Kamrani, M ; Sayedsalehi, S ; Navi, K ; Sharif University of Technology
Quantum dots cellular automata is a new computing method in the nanotechnology that has considerable features such as low power, small dimension and high speed switch. A QCA device stores logic based on the position of individual electrons. The fundamental logic elements in QCA are the majority (Fig.1 (a)) and inverter gates (Fig.1 (b)) that operate based on the Coulomb repulsion between electrons 
Compensation method for multistage opamps with high capacitive load using negative capacitance, Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 63, Issue 10 , 2016 , Pages 919-923 ; 15497747 (ISSN) ; Sharif Bakhtiar, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
It is shown that negative capacitance (NC) circuits can be systematically used to improve the gain-bandwidth product of the operational amplifiers (opamps). The NC circuit moves the nondominant pole of the opamp to higher frequency by decreasing the parasitic capacitance of the critical node. The impedance at the input of the NC circuits is neither purely capacitive nor negative at all frequencies. A design guide is presented by deriving the circuit model for a conventional NC circuit and investigating the extent of the improvement that can be achieved in a circuit by the use of the NC circuit. The model is then used to present the design guide for widebanding the multistage opamps with...
A low-power dynamic comparator for low-offset applications, Article Integration ; Volume 69 , 2019 , Pages 23-30 ; 01679260 (ISSN) ; Saeidi, R ; Sachdev, M ; Sharifkhani, M ; Sharif University of Technology
Elsevier B.V 2019
In this paper, a low-power method for double-tail comparators is introduced. Using the proposed method, the power consumption of the pre-amplifier which is the dominant part is reduced considerably. Thanks to this method, the pre-amplifier is not able to draw more than required amount of power, therefore, the power is saved. Post layout and corner simulation results show the power consumption is reduced by about 40%. Moreover, several Monte-Carlo (M) simulations suggest the proposed method results in about 20% offset reduction at the cost of 5% area and 10% speed degradation. © 2019 Elsevier B.V
Optimum supply and threshold voltages and transistor sizing effects on low power SOI circuit design, Article APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 4 December 2006 through 6 December 2006 ; 2006 , Pages 1394-1398 ; 1424403871 (ISBN); 9781424403875 (ISBN) ; Jafargholi, A ; Sargazi Moghadam, H ; Nayebi, M. M ; Sharif University of Technology
In this work we introduce new model for energy-delay product and the performance of 80-nm SOI-CMOS circuits for the range of Vdd=0.1-1.5V and Vth=0-0.8V, are analyzed to find optimal Vdd and Vth BSIMSOI3.3 model (level 57) is used to verify the answers. We show that Energy-Delay Product (EDP) isn't appropriate metric for gate sizing problem. And a new design metric is introduced as a generalization of EDP. This metric is used to determine the transistor sizing for complex circuits based on the specified delay and energy constrains. In this case, unlike the conventional energy delay product metric, delay and energy can be considered with different emphasis. The complete design flowcharts and...
A low-power 10-Bit 40-MS/s pipeline ADC using extended capacitor sharing, Article Proceedings - IEEE International Symposium on Circuits and Systems ; 1- 5 June , 2014 , pp. 1147-1150 ; ISSN: 02714310 ; Sharifkhani, M ; Shabany, M ; Sharif University of Technology
This paper describes a new capacitor sharing technique for pipeline ADCs. It enables power reduction of the first and second MDACs simultaneously. The presented noise and power analysis shows that the proposed method is about 30% more efficient than the conventional one in terms of the first and second MDACs power dissipation. A 10-bit 40MS/s pipeline ADC employing the proposed technique was designed in 90-nm CMOS technology achieving a power consumption of 4.2 mW
A system-level design method for RF receiver front-end with low power consumption, Article Analog Integrated Circuits and Signal Processing ; 2021 ; 09251030 (ISSN) ; Atarodi, M ; Sadughi, S ; Sharif University of Technology
Due to wireless communication’s rapid growth, the need for low power integrated transceivers is increasing. The receiver power is a major limiting factor, and the radio frequency (RF) front-end is often its significant power consuming part. Therefore, system-level design in which the overall specifications are distributed among RF front-end building blocks such that the minimum total power is consumed is crucial. A complete system-level design method for a low power RF front-end is presented in this paper. For this purpose, the performance of each block is modeled by its current and overdrive voltage. An analytical associated with a search-based optimization technique is employed to derive...
A compact versatile microbial fuel cell from paper, Article ASME 2013 11th Int. Conf. on Fuel Cell Science, Eng. and Technology Collocated with the ASME 2013 Heat Transfer Summer Conf. and the ASME 2013 7th Int. Conf. on Energy Sustainability, FUELCELL 2013 ; 2013 ; 9780791855522 (ISBN) ; Hashemi, N ; Hashemi, N ; Sharif University of Technology
Microbial fuel cells (MFCs) have been a potential green energy source for a long time but one of the problems is that either the technology must be used on a large scale or special equipment have been necessary to keep the fuel cells running such as syringe pumps. Paper-based microbial fuel cells do not need to have a syringe pump to run and can run entirely by themselves when placed in contact with the fluids that are necessary for it to run. Paper-based microbial fuel cells are also more compact than traditional MFCs since the device doesn't need any external equipment to run. The goal of this paper is to develop a microbial fuel cell that does not require a syringe pump to function. This...
A 1-mW current reuse quadrature RF front-end for GPS L1 band in 0.18μm CMOS, Article 2012 19th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2012, Seville, Seville, 9 December 2012 through 12 December 2012 ; 2012 , Pages 157-160 ; 9781467312615 (ISBN) ; Fotowat Ahmady, A ; Jenabi, M ; Sharif University of Technology
A new low-power current reuse topology is proposed for the GPS receiver's RF front-end that combines the higher conversion gain and suppressed noise figure characteristics of cascade structures with the low power consumption of stacked architectures. The presented circuit, called 1.5-stage LMV cell, consists of LNA, Mixer and VCO (LMV) in such a formation that boosts LNA gain and suppresses mixer's noise figure by cascading the two stages while reusing their currents in the two stacked quadrature VCOs and placing the mixer's upper tree switches at the vicinity of on-off regions. The circuit is designed and its layout is generated in TSMC 0.18μm CMOS technology. Post-layout simulations using...
A new spectrum sensing circuit for cognitive radio applications, Article Proceedings - CIMSim 2011: 3rd International Conference on Computational Intelligence, Modelling and Simulation, 20 September 2011 through 22 September 2011, Langkawi ; 2011 , Pages 404-407 ; 9780769545622 (ISBN) ; Forooraghi, K ; Atlasbaf, Z ; Ahmadi, A. F ; Sharif University of Technology
Fast, accurate and efficient sensing is of important aspects in cognitive radio technology. A new sensing circuit is proposed using a phase frequency detector for cognitive radio applications. Using this method, spectral sensing can be done in a very short time by a low cost, low power circuit, compared with available implemented methods. The PFD circuit resolves different frequencies without the need of variable filter bandwidth or the banks of filters. Also it accelerates sensing procedure because of short time needed to detect the signal. Simulations show the accurate operation of this method and comparison with other methods shows faster sweep rates
A low cost circuit level fault detection technique to full adder design, Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011, Beirut ; 2011 , Pages 446-450 ; 9781457718458 (ISBN) ; Fazeli, M ; Hessabi, S ; Miremadi, S. G ; Sharif University of Technology
This paper proposes a Low Cost circuit level Fault Detection technique called LCFD for a one-bit Full Adder (FA) as the basic element of adder circuits. To measure the fault detection coverage of the proposed technique, we conduct an exhaustive circuit level fault injection experiment on all susceptible nodes of a FA. Experimental results show that the LCDF technique can detect about 83% of injected faults while having only about 40% area and 22% power consumption overheads. In the LCDF technique, the fault detection latency does not affect the latency of the FA, since the error detection is done in parallel with the addition
A low-power current reuse CMOS RF front-end for GPS applications, Article 2011 IEEE International RF and Microwave Conference, RFM 2011 - Proceedings, 12 December 2011 through 14 December 2011, Seremban ; 2011 , Pages 416-419 ; 9781457716294 (ISBN) ; Fotowat Ahmady, A ; Sharif University of Technology
A very low-power RF front-end based on a new current reuse QLMV cell (Quadrature VCO-LNA-Mixer) is proposed for GPS applications. The front-end, designed in 0.18μm CMOS technology, provides improved performance characteristics while consuming only 1 mA current. Simulation results are presented and compared with recently published works in the field
Opportunities for embedded software power reductions, Article Canadian Conference on Electrical and Computer Engineering ; 2011 , Pages 000763-000766 ; 08407789 (ISSN) ; 9781424497898 (ISBN) ; Goudarzi, M ; Sharif University of Technology
While performance and power consumption of processors present a classic trade-off in designing embedded hardware, software can be optimized in favor of both performance and energy. We evaluate the impact of optimizations at different stages of designing embedded software. We show that algorithm choice and compiler optimizations aimed at improving performance can also reduce energy consumption of an embedded processor. We also propose energy-aware compilation guidelines which can further reduce energy consumption without performance penalties. Our experimental results show that up to 85% energy reduction and 89% performance improvement can be achieved by these techniques
Zero-power mismatch-independent digital to analog converter, Article AEU - International Journal of Electronics and Communications ; Volume 69, Issue 11 , 2015 , Pages 1599-1605 ; 14348411 (ISSN) ; Sharifkhani, M ; Sharif University of Technology
Elsevier GmbH 2015
A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method
An audio band low voltage CT-ΔΣ modulator with VCO-based quantizer, Article 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 2011, 11 December 2011 through 14 December 2011 ; December , 2011 , Pages 232-235 ; 9781457718458 (ISBN) ; Sharifkhani, M ; Sharif University of Technology
This paper presents the design and implementation of a low power, low voltage, continuous time delta sigma modulator for audio band in 90 nm CMOS technology. A VCO-based integrator and quantizer are used. Inherent dynamic element matching (DEM) of the quantizer eliminates the need for explicit DEM logic which results in a short excess-delay and power saving. Simulation results show that the modulator achieves 78 dB SNDR and 87 dB SNR in a 20 kHz input bandwidth and dissipates 106 μW from 1 V supply. The power consumption for different parts is discussed
An accurate low-power DAC for SAR ADCs, Article 59th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2016, 16 October 2016 through 19 October 2016 ; 2017 ; 15483746 (ISSN); 9781509009169 (ISBN) ; Khorami, A ; Sharifkhani, M ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2017
A highly energy-efficiency switching procedure for the capacitor-splitting digital-To-Analog converter (DAC) is presented for successive approximation register (SAR) analogue-To-digital converters (ADCs). In this procedure, the MSB capacitor is divided into its binary constituents. All output digital bits, except the least significant bit (LSB), is determined using reference voltage (Vref), while the common-mode voltage (Vcm) is used to determine the LSB. Therefore, the precision of the proposed SAR ADC is independent of the precision of Vcm except in the LSB. This method reduces the area by 75% compared to the conventional binary weighted DAC and reduces the switching energy by 96.89%. ©...
Towards a reliable modulation and encoding scheme for internet of things communications, Article 13th IEEE International Conference on Application of Information and Communication Technologies, AICT 2019, 23 October 2019 through 25 October 2019 ; 2019 ; 9781728139005 (ISBN) ; Safaei, B ; Talaei, K ; Hosseini Monazzah, A. M ; Ejlali, A ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc 2019
As the emergence of Internet of Things (IoT) brings the realization of ubiquitous connectivity ever closer, our reliance on these applications gets more important. Nowadays, such connected devices could be found everywhere, from home appliances to industrial control systems and environmental monitoring applications. One of the main challenges in IoT infrastructures is that of reliability, which emboldens itself in the context of Low-power and Lossy Networks (LLN) as they are inherently prone to packet loss as a result of their environmental and design constraints. Therefore, reliability of IoT devices becomes crucially important. With communication, the most important consideration in these...