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    A novel hardware implementation for joint heart rate, respiration rate, and gait analysis applied to body area networks

    , Article Proceedings - IEEE International Symposium on Circuits and Systems ; 2013 , Pages 1889-1892 ; 02714310 (ISSN) ; 9781467357609 (ISBN) Khazraee, M ; Zamani, A. R ; Hallajian, M ; Ehsani, S. P ; Moghaddam, H. A ; Parsafar, A ; Shabany, M ; Sharif University of Technology
    2013
    Abstract
    Continuous and remote monitoring of vital health-related and physical activity signs of a patient is one of the most important technology-oriented applications to monitor the health-care of ill individuals. In this paper, an innovative framework for a wireless Body Area Network (BAN) system, based on the IEEE 802.15.6 standard, with three types of sensors is proposed and implemented. These include Electrocardiogram (ECG), Force Sensitive Resistor (FSR) and Gyroscope. The proposed design is a novel implementation of an embedded system for the real-time processing and analyzing of the ECG signal, gait phases, and detection of the respiration rate from the ECG signal, by means of small... 

    A compact 8-bit AES crypto-processor

    , Article 2nd International Conference on Computer and Network Technology, ICCNT 2010, 232010 through 25 April 2010 ; April , 2010 , Pages 71-75 ; 9780769540429 (ISBN) Haghighizadeh, F ; Attarzadeh, H ; Sharifkhani, M ; Sharif University of Technology
    2010
    Abstract
    Advance Encryption Standard (AES), has received significant interest over the past decade due to its performance and security level. In this paper, we propose a compact 8-bit AES crypto-processor for area constrained and low power applications where both encryption and decryption is needed. The cycle count of the design is the least among previously reported 8-bit AES architectures and the throughput is 203 Mbps. The AES core consumes 5.6k gates in 0.18 μm standard-cell CMOS technology. The power consumption of the core is 49 μW/MHz at 128 MHz which is the minimum power reported thus far  

    Shrinking FPGA static power via machine learning-based power gating and enhanced routing

    , Article IEEE Access ; Volume 9 , 2021 , Pages 115599-115619 ; 21693536 (ISSN) Seifoori, Z ; Asadi, H ; Stojilovic, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2021
    Abstract
    Despite FPGAs rapidly evolving to support the requirements of the most demanding emerging applications, their high static power consumption, concentrated within the routing resources, still presents a major hurdle for low-power applications. Augmenting the FPGAs with power-gating ability is a promising way to effectively address the power-consumption obstacle. However, the main challenge when implementing power gating is in choosing the clusters of resources in a way that would allow the most power-saving opportunities. In this paper, we take advantage of machine learning approaches, such as K-means clustering, to propose efficient algorithms for creating power-gating clusters of FPGA...