Sharif Digital Repository

A new nonlinear Time to Digital Converter (TDC) based on time difference amplification is the proposed. A new gain compensation method is presented to expand the DR of conventional × 2 Time Amplifiers (TAs). Instead of conventional gain compensation approach based on changing strength of current sources, the proposed technique uses current difference which results more stable gain over wider DR. In order to avoid two different paths of the stages, a sign bit detection part is the proposed at the front of the TDC to allow using one path of stages for both positive and negative input time differences. As a result, the most advantages of the proposed TDC are its high resolution, wide DR, and... 

In this paper, a low power receiver for medical implant communication service (MICS) is presented. Low power design is vital in the MICS applications since the implanted chip has to work for a long time without the need to change its battery. As a result, a merged N-path low noise amplifier (LNA) and mixer block is proposed. In this structure, the LNA and down-conversion mixer share a transconductance to lower the overall power consumption. An N-path feedback is utilized around the shared transconductance not only to improve the LNA selectivity and relax the linearity requirements but also to downconvert the radio frequency (RF) component and create the intermediate frequency (IF) signal. In... 

In this paper, we present a novel routing algorithm in order to avoid deadlock and packet dropping. In our proposed algorithm the network-on-chip (NoC) is capable of tolerating faults in presence of control faults in combinational parts of routers. In addition, by modifying the functionality of the router, the router is enabled to test its own, as well as the preceding router's functionality based on the routing algorithm, destination address and previous router's situation. Each router recognizes the faulty neighbor and announces it to successive routers. In this scheme no extra packets will be generated. We analyze the effects of our method on latency, power consumption and drop rate. Our... 

A new low-power current reuse topology is proposed for the GPS receiver's RF front-end that combines the higher conversion gain and suppressed noise figure characteristics of cascade structures with the low power consumption of stacked architectures. The presented circuit, called 1.5-stage LMV cell, consists of LNA, Mixer and VCO (LMV) in such a formation that boosts LNA gain and suppresses mixer's noise figure by cascading the two stages while reusing their currents in the two stacked quadrature VCOs and placing the mixer's upper tree switches at the vicinity of on-off regions. The circuit is designed and its layout is generated in TSMC 0.18μm CMOS technology. Post-layout simulations using... 

Continuous shrinking of transistor size to provide high computation capability along with low power consumption has been accompanied by reliability degradations due to e.g., aging phenomenon. In this regard, with huge number of configuration bits, Field-Programmable Gate Arrays (FPGAs) are more susceptible to aging since aging not only degrades the performance, it may additionally result in corrupting the configuration cells and thus causing permanent circuit malfunctioning. While several works have investigated the aging effects in Look-Up Tables (LUTs), the routing fabric of these devices is seldom studied - even though it contributes to the majority of FPGAs' resources and configuration... 

A phase frequency detector (PFD) with a very low dead zone is proposed which is based on a configuration adaptable to both CMOS or carbon nano-tube transistors (CNTFETs). In the first step the proposed configuration is designed using CMOS transistors, and then CNTFETs are substituted to improve the speed and reduce the propagation delay. The proposed PFD in addition to very low dead zone, has low power consumption and high frequency range of operation, which are achieved as a result of the elimination of the reset path. The simulation results based on 32 nm technology for CNTFET and 180 nm technology for CMOS, illustrate that CNTFET-based proposed circuit dissipates 2 µW and has frequency of... 

Nowadays, ultra-wideband (UWB) communication systems are in focus because of their attractive features such as high capacity, low power consumption and robustness against fading. On the other hand, spectrally-encoded spread-time (SE/ST) systems with superior ability on interference suppression provide proper multiuser efficiency over UWB channels. Coherent SE/ST code division multiple access (CDMA) systems are widely addressed in the literature requiring accurate channel estimation and high implementation complexity. In this paper we propose multi-level SE/ST CDMA system with non-coherent detection and simple receiver structure. Our results demonstrate the effect of signal to noise ratio... 

A four stage LC-ring oscillator is presented. Eight different phases are generated in which there in 45 degrees phase difference between consecutive outputs and direction of phases is defined. Nmos capacitors in parallel with constant capacitors are used for coupling between stages. The control voltage is applied to Pmos varactors to adjust the oscillation frequency. The advantages of this structure are the rather small inductors size, low power consumption, and tuning curve linearity. The proposed structure is simulated in 0.18um CMOS technology. Power consumption for each stage is 4.8mW from a 1.8B supply. The proposed VCO has a phase noise of -121dBc/Hz at 1MHz offset from the center... 

High reliability and low power consumption are among the major requirements in design of wireless sensor networks (WSNs). In this paper, a multi-objective problem is formulated as a Joint Power consumption and data Reliability (JPR) optimization problem. For this purpose, a connected dominating set (CDS)-based topology control approach is proposed. Our objective is to self-organize the network with minimum interference and power consumption. We consider the power changes into a topology with minimum CDS infrastructure subject to connectivity constraints. Since this problem is NP-hard, it cannot be dealt with using polynomial-time exact algorithms. Therefore, we first present a genetic... 

High reliability and low power consumption are the critical objectives in wireless networks and the network topology is an effective issue in these objectives. This paper investigates these two objectives in the wireless multi-hop networks simultaneously. For this purpose, a connected dominating set CDS-based topology control approach is proposed. In this approach a distributed topology control algorithm with different power adjustment measures is suggested. Our goal is to self-organize this network with minimum interference and power consumption subject to connectivity preservation. Unlike many reliability enhancement algorithms, the proposed mechanism does not compromise power consumption.... 

Scaling of CMOS devices being aggressively decreasing by reduce of transistor dimensions. However, such level of integration leads to many physical limit and transistors cannot get much smaller than their current size. Quantum-dot Cellular Automate is a novel technology which significantly reduces physical limit of CMOS devices implementation, thus, it can be an appropriate candidate to be substituted for CMOS technology. In addition to high integration density of QCA circuits, other unique specifications such as high speed and low power consumption encourage researchers to utilize this technology instead of CMOS technology. In this paper, a new layout of XOR gate is presented in QCA... 

Simulation of large-scale nonlinear dynamical systems on hardware with a high resemblance to their mathematical equivalents has been always a challenge in engineering. This paper presents a novel current-input current-output circuit supporting a systematic synthesis procedure of log-domain circuits capable of computing bilateral dynamical systems with considerably low power consumption and acceptable precision. Here, the application of the method is demonstrated by synthesizing four different case studies: 1) a relatively complex 2-D nonlinear neuron model; 2) a chaotic 3-D nonlinear dynamical system Lorenz attractor having arbitrary solutions for certain parameters; 3) a 2-D nonlinear Hopf... 

The use of Solid State Drives (SSDs) has been increased in storage systems due to high performance and low power consumption. However, some inherent properties of SSDs result in different behavior for SSDs in comparison with Hard Disk Drives (HDDs). As an inherent property, the Bit Error Rate (BER) of SSDs increases, when the number of Program/Erase (P/E) cycles arises. This increment leads to two effects in an array of SSDs during its operation: (1) different BER on different SSDs of the system (SSD-variant BER), and (2) different BER in different time moments (time-variant BER). With respect to these two effects, the reliability evaluation of SSD-based RAIDs would be different from... 

Quantum-dot Cellular Automata (QCA) is a very interesting nano-scale technology. Extremely small feature size and ultra-low power consumption are the most important features of QCA compared to CMOS. Counters are considered as one of the most fundamental components in sequential circuits. Previous QCA synchronous counters (QSCs) have been designed and simulated using two methods. In the first method, QSCs utilize direct mapping flip-flop designs in CMOS technology to QCA. In the second method, QSCs are designed with the inherent capability of QCA technology. Despite being attractive, mentioned approaches have constraints (i.e. long wire length and area issues). In this brief, design and... 

This paper presents a circuit level soft error-tolerant-technique, called RRC (Robust Register Caching), for the register file of embedded processors. The basic idea behind the RRC is to effectively cache the most vulnerable registers in a small highly robust register cache built by circuit level SEU and SET protected memory cells. To decide which cache entry should be replaced, the average number of read operations during a register ACE time is used as a criterion to judge. In fact, the victim cache entry is one which has the maximum read count. To minimize the power overhead of the RRC, the clock gating technique is efficiently exploited for the main register file resulting in... 

A novel low power with high performance low current comparator is proposed in this paper which comprises of low input impedance using a simple biasing method. It aimed for low power consumption and high speed designs compared with other high speed designs. The simulation results from HSPICE demonstrate the propagation delay is about 0.7 ns and the average power consumption is 130 μW for 100 nA input current at supply voltage of 1.8 V using 0.35 micron CMOS technology. © 2009 IEEE  

High reliability, high performance, low power consumption are the main objectives in the design of NoCs. These three design objectives are mostly conflicting and should be considered simultaneously in order to have an optimal design. This paper proposes a method based on duplicating the virtual channels of each NoC node as well as parity codes to prevent SEUs from producing erroneous data. The method is compared with two widely used SEU-tolerant methods i.e., the Switch to Switch and the End to End flow control methods, in terms of reliability, power consumption and performance. A flit level VHDL-based simulator and Synopsys Power Compiler tool have been used to extract experimental results....