Sharif Digital Repository

Considering ever expanding applications of embedded systems in all aspects of human life, reliability and fault tolerance of these systems have become vital. To increase the reliability in a microprocessor as the most critical component of an embedded system, one may notice the essential role that is offered by its register bank. In fact the register bank is the most critical subcomponent of an embedded system, greatly affecting the reliability of the overall system. The operation of the embedded system is further critically affected through optimal and efficient usage of power as most systems relay on battery. In this project, to evaluate the availability of register banks various... 

Low power and high speed analog-to-digital converters (ADCs) are the key elements of communication and computing systems. There are several ADC structures such as delta-sigma, flash, pipeline, and successive approximation register (SAR) for different applications, albeit SAR ADCs are natural candidates of onchip designs for their low power and scalability benefits. Nowadays, SAR ADCs are widely being used in low-power moderate-resolution applications which need several tens of MS/s to low GS/s sampling rates. By virtue of the technology scaling power consumption of digital parts of a SAR ADC is reduced significantly. As a result, in a SAR ADC the power consumption of the digital-to-analog... 

ADC is one of the key functional blocks of any mixed signal system and therefore must be optimally designed concerning power, performance, resolution and silicon area. Among different architectures have been employed up to now, successive approximation register ADCs are known as the ones with lower power, more simplicity and lower sampling rate. Benefiting from scaling down the CMOS technology results in higher sampling rate and lower power SAR ADCs replacing other types of ADCs. To achieve the desired ADC performance, efforts are usually focused on the improvement of circuit techniques as well as on the introduction of new or combinational architectures based on SAR ADCs. This thesis aims... 

Due to recent prevalence of error resilient applications (e.g., multimedia, artificial intelligence, etc.), approximate computing (AC) has become a promising paradigm for low power and high performance designs. A significant amount of research in AC has been focused on improving the power and performance by approximating arithmetic units. However, memories i) are also a major contributor to the overall energy consumption (e.g., 30% to 60%) and response time of a system, and ii) result in perceivable quality degradation when used approximately. In this thesis, we employ the predictability potential of embedded systems in order to enable quality-aware exploitation of the advantages of the... 

From the cache of the personal computers to the main memory unit of SOCs, medical and wearable chips, Static Random Access Memory (SRAM) is widely utilizes. Preferable performance for SRAM varies with regard to the operating field. For instance, high speed access and performance is emphasized in the design of the cache for PCs. In contrast, power consumption and the area of the memory are the key design considerations for SOCs. Hence, the field in which SRAM is used, should be thoroughly studied. SOCs and medical chips suffer limitations in design due to using batteries as the source of energy and SRAMs consume a significant part of total power and occupy a large area on these chips. One of... 

RT-level techniques are one of the most important categories of techniques employed for decreasing power consumption in digital systems. These techniques are usually applied in the HDL description of the system, however some of them are applicable automatically by the synthesis tools. Some of the most commonly used RT-level techniques include Operand isolation, Clock gating, Concurrency & Redundancy, Pre-computation and Pipeline for low power. However these techniques have been mostly employed in ASIC designs, and FPGAs have scarcely been addressed. Application of these techniques on FPGAs might need special considerations, since resources on FPGAs are inherently different than their ASIC... 

In recent years, the possibility of building large systems on chip, called SoC is provided. By scaling the technology, designing Socs will face numerous challenges. The Noc paradigm, has resolved many of the SoC’s problems, by deploying network properties in the structures of on chip interconnections. Today, with advances in the semiconductor industry, we can implement broadband wireless antennas, which are integrated on chip. Such NoCs are called WNoC. Due to immaturity of WNoCs, there still exist big challenges, providing routing algorithm and controlling shared medium via MAV layers, for them. In this project, we will provide a routing algorithm based on tag switching, and then, after...