Sharif Digital Repository

A low voltage bandgap reference (BGR) in CMOS technology, with high power supply rejection ratio (PSRR) is presented. The proposed circuit uses a regulated current mode structure and some feedback loops to reach a low voltage, low power and high PSRR voltage reference. The circuit was designed and simulated in 0.25um CMOS technology, with a power supply of 1 volt. The results show PSRR is below -70dB at 1MHz and the output voltage variation versus temperature (0-70) is less than 0.3%. This circuit shows robustness against process variation  

This research focused on making novel low-voltage SnO2 varistors by CuO addition on conventional high-voltage SnO2 varistors. Moreover, the withstand surge capability of samples was studied. The results showed that CuO addition enhances grain growth of SnO2 and coarse-grained SnO2 varistors with simple microstructures were acquired in 1 mol% CuO-doped sample. This coarse-grained SnO2 varistor presented a high nonlinear coefficient (23) and low leakage current density (23 µA/cm2) with low breakdown field value of 0.6 kV/cm. Despite the large grain size, the low residual voltage ratio (2.3) was obtained for this sample compared to the CuO-free sample. The decrease in grain electric resistivity... 

Up to now, attempts for developing coarse-grained SnO2-based varistors which exhibit high nonlinearity property at lower voltage have become a challenge without any prominent result because of its unknown grain growth mechanism. In this study, the effect of CuO addition to SnO2-based varistors as a grain growth enhancer additive on microstructural development, grain growth kinetics, and electrical properties was investigated. The characterization of grain growth kinetics showed that CuO addition encouraged grain growth and enhanced the grains size as it could be seen in the activation energy which decreased from 594 kJ/mol to 364 kJ/mol. In the samples with a low amount of CuO, the solute... 

Currently, there are no studies investigating the issue of speed optimization of Gain-Boosted Cascode Amplifier in low voltage applications. This is mainly because of the complicated transfer function of high-swing Gain-Boosted Cascode Amplifier structures. This paper proposes a novel and generic model for this amplifier and presents a thorough analysis of its behavior. The aim of this optimization is to eliminate the well-known slow timing component in the step response and obtain the minimum achievable settling time. An ultra high-speed amplifier is presented finally  

A novel current reference with low temperature and supply sensitivity and without any external component has been developed in a 0.25 μm mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit similar to a beta multiplier. An NMOS transistor in triode region has been used in place of a resistor in conventional beta multiplier to achieve a current which has a negative temperature coefficient and only oxide thickness dependent. The BGR voltage has a positive temperature coefficient to cancel the negative temperature coefficient of the beta multiplier. The simulation results using Bsim3v3 model show max-to-min fluctuation of less than 1 % over a... 

A new, ultra low-voltage, linear CMOS OTA will be described. A 4th order, 18 MHz low pass Butterworth Gm-C filter has been designed with this new OTA stage for video applications. In this filter a new, fully digital approach has been used for frequency tuning. The THD of the filter for input signal 0.5 VPPis better than -60 dB. All of circuits are designed based on 0.25 um CMOS process technology with a single 1-volt power supply  

A low voltage high speed class AB op-amp with new structure is presented. The proposed op-amp has been designed to drive a large capacitive load as large as 10 pf dedicated for high-resolution high-speed pipelined analog to digital converters. Consuming comparatively low power about 6 mw, the proposed class AB op-amps has an output swing of 2.6 Vpp from a single supply of 1.5 volt. It has been observed that this op-amp can be suitable for a 1.5 volt 13-bit Pipelined A/D with sampling rate of 60 MS/S. This op-amp is to be fabricated in standard 0.18u CMOS technology  

This paper presents a low voltage low noise open loop automatic amplitude control method for voltage-controlled oscillators (VCO's). In this method a feedback mechanism keeps the VCO at its optimum amplitude over temperature and process variations and then the loop is broken to avoid noise injection form the control circuitry to the VCO. The loop does not add extra noise to the VCO. Based on the proposed method, a low voltage low noise LC-VCO was designed for a low phase noise application in TSMC 0.18 micron RFCMOS technology. Simulations show considerable improvement in the phase noise with the application of the proposed method  

A new technique for improving the performance of low-voltage folding ADC's by extending the input range is presented. It is shown that by using both PMOS and NMOS differential pairs in the folding blocks, the overall input voltage range of the ADC can be increased to rail-to-rail. A novel self-adjustment method is also introduced to compensate for the different input-output characteristics of PMOS and NMOS differential pairs. A low voltage 8-bit 80 MSample/s folding/interpolating ADC is then designed and fabricated in a 0.18 μm CMOS process. Operating with a supply voltage as low as 1.2 V, measurements show an INL below ±0.55 LSB, SNDR of 43.5 dB at 80 MHz Sampling Frequency and power... 

Limitations in operation of analog switches at very low voltages have caused many problems in design of these types of switched capacitor circuits and data converters. In this paper by modifying a recently proposed clock boosting circuit, we could obtain a new structure with better performance for very low voltage circuits. This method requires simpler digital circuits in comparison with previously reported structures, as well as less number of transistors and smaller chip area. This method can be used for sampling the full swing signals with supply voltages as low as 0.4 volt. © 2008 IEEE  

This paper presents a new class AB circuit for current-mode signal processing. These current mirrors are especially designed for advanced CMOS technologies and low-voltage high-speed applications. As an example two current amplifiers with a gain of 2, settling time of less than 6ns and current consumption of 500μA are designed and simulated. ©2006 IEEE  

The brushless doubly fed induction generator (BDFIG) has been proposed as a viable alternative in wind turbines to the commonly used doubly fed induction generator (DFIG). The BDFIG retains the benefits of the DFIG, i.e. variable speed operation with a partially rated converter, but without the use of brush gear and slip rings, thereby conferring enhanced reliability. As low voltage ride-through (LVRT) performance of the DFIG-based wind turbine is well understood, this paper aims to analyze LVRT behavior of the BDFIG-based wind turbine in a similar way. In order to achieve this goal, the equivalence between their two-axis model parameters is investigated. The variation of flux linkages,... 

In this paper a new low-voltage two-stage class-AB line driver for ADSL applications is presented. The new proposed line-driver consists of only two stages with a new method to control the quiescent current of the output stage. The low-voltage full-CMOS high-linear line driver shows -77 dB THD for a load as low as 20 ohms. The line driver has variable gain, attenuating the input signal from 0dB to -14dB with 2dB steps. The peak to peak differential output swing is 4.2-V from a 2.5-V Supply voltage in a 0.25um standard CMOS technology  

A very low power CMOS, 1.5V, 2.5GHz prescaler was designed. Implemented in 0.25u standard CMOS technology, this prescaler can operate up to 3GHz range. The prescaler consists of three delay flip flops (DFF) that work synchronously with RF sinusoidal clock and divides by 4 or 5 according to control signal  

A 1.5-V single supply, second order continuous-time bandpass filter, on a 0.6μm standard CMOS process is designed. The THD of the transconductor for a 0.7Vpp input, is -50dB at 10-MHz. In the proposed transconductor structure, the whole circuit, apart from a dc level-shifter based on a voltage doubler, is biased by a single 1.5-V supply. Due to this structure, a high current voltage doubler is not required and the whole filter draws less than 70μm current from this doubler making an on-chip voltage doubler feasible. Also, a new linear common-mode detector with high-frequency response is designed to stabilize the output common-mode voltage. © 2002 IEEE  

In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18μm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25μw quiescent power with 2GHz bandwidth and 1.5% THD  

Uncoordinated adoption of plug-in electric vehicles (PEVs) imposes further load on the distribution network, and therefore may result in disruptive impacts on the grid. Transactive coordination of PEVs has been introduced as an effective approach to mitigate these negative consequences. This paper furthers efforts enabling PEVs to participate in a real-time retail electricity market under a transactive energy (TE) paradigm. In this regard, PEV owners will estimate their willingness to pay/accept using a user-friendly strategy and submit the estimated values to the retail market operator. Then using a network-constrained market clearing mechanism, the clearing prices, i.e., dual variables of... 

With proliferation of single-phase rooftop photovoltaic (PV) panels, phase balancing in low voltage (LV) distribution feeders becomes the point of concern. In this way, identification of the hosting phase of connected single-phase customers and PV panels is a prerequisite. This paper proposes an optimization model for the phase identification problem. The objective is to minimize the summation of the absolute error between estimated and measured variables. Smart meters (SMs) data including active and reactive power absorptions/injections, nodal voltage magnitudes, and network configuration data form the input of the model. Potential errors in the input data are captured in the model while... 

A realistic and practicable modeling of unbalanced distribution networks (DNs) is the missing link in most studies undertaken in these networks, e.g., optimal power flow (OPF), energy markets, etc. To address the issue, this letter proposes an unbalanced linear three-phase four-wire power flow (PF) model based on current injection equations at nodes. Also, the ZIP representation is considered for loads. The model can be easily generalized for unbalanced three-wire networks with minor changes and assumptions. Hence, the scope of the proposed method can be extended to cover both low-voltage and medium-voltage DNs. The performance of the proposed model is verified through simulations on two... 

A low voltage current mode sample and hold (S/H) in 0.18μm technology with 1.5v supply voltage is presented. This S/H has 12-bit linearity, i.e., gain and nonlinearity errors of S/H are less than 0.02μA for 100uA input current. Maximum sampling rate for this structure is 100 MHz (using double sampling technique). © 2005 IEEE