Sharif Digital Repository

This paper presents the first ASIC implementation of an LR algorithm which achieves ML diversity. The VLSI implementation is based on a novel hardware-optimized LLL algorithm that has 70% lower complexity than the traditional complex LLL algorithm. This reduction is achieved by replacing all the computationally intensive CLLL operations (multiplication, division and square root) with low-complexity additions and comparisons. The VLSI implementation uses a pipelined architecture that produces an LR-reduced matrix every 40 cycles, which is a 60% reduction compared to current implementations. The proposed design was synthesized in both 130μm and 65nm CMOS resulting in clock speeds of 332MHz and... 

This paper presents a VLSI architecture of a novel softoutput K-Best MIMO detector. The proposed detector attains low computational complexity using three improvement ideas: relevant discarded paths selection, last stage on-demand expansion, and relaxed LLR computation. A deeply pipelined architecture for a soft-output MIMO detector is implemented for a 4x4 64-QAM MIMO system realizing a peak throughput of 655Mbps, while consuming 174K gates and 195mW in 0.13um CMOS. Synthesis results in 65nm CMOS show the potential to support a sustained throughput up to 2Gbps achieving the data rates envisioned by emerging IEEE 802.16m and LTE-Advanced wireless standards  

This paper presents a prototype of a high-throughput 4x4 64-QAM MIMO receiver consisting of a channel matrix QR decomposition, a soft-output K-Best MIMO detector and a Convolutional Turbo Code decoder. The proposed MIMO receiver provides low processing latency and a pipelined architecture scalable to a larger number of antennas and constellation order. Therefore, it is suitable for LTE-Advanced and IEEE 802.16m broadband wireless standards. A rapid prototyping platform interfacing MATLAB with Xilinx ISE was used in the development of the 4x4 64-QAM MIMO receiver. The receiver utilizes 96% of the slice LUTs and 78% of slice registers on Virtex-5 FX130T FPGA, operating at a maximum frequency... 

To cope with the unprecedented growth of mobile data traffic, we investigate the performance gains obtained from unifying coverage-centric 4G mobile networks and capacity-centric fiber-wireless (FiWi) broadband access networks based on data-centric Ethernet technologies with resulting fiber backhaul sharing and WiFi offloading capabilities. Despite recent progress on backhaul-aware 4G studies with capacity-limited backhaul links, the performance-limiting impact of backhaul latency and reliability has not been examined in sufficient detail previously. In this paper, we evaluate the maximum aggregate throughput, offloading efficiency, and in particular, the delay performance of FiWi enhanced...