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A high speed, high resolution, low voltage currentmode sample and hold
, Article IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, 23 May 2005 through 26 May 2005 ; 2005 , Pages 1417-1420 ; 02714310 (ISSN) ; Bakhtiar, M. S ; Sharif University of Technology
2005
Abstract
A low voltage current mode sample and hold (S/H) in 0.18μm technology with 1.5v supply voltage is presented. This S/H has 12-bit linearity, i.e., gain and nonlinearity errors of S/H are less than 0.02μA for 100uA input current. Maximum sampling rate for this structure is 100 MHz (using double sampling technique). © 2005 IEEE
Circuit and system design for an 860-960 MHz RFID reader front-ends with Tx leakage suppression in 0.18 - μm CMOS technology
, Article International Journal of Circuit Theory and Applications ; Volume 40, Issue 9 , MAR , 2012 , Pages 957-974 ; 00989886 (ISSN) ; Atarodi, S. M ; Luong, H. C ; Sharif University of Technology
Wiley
2012
Abstract
This paper presents an RF Front-END for an 860-960thinspaceMHz passive RFID Reader. The direct conversion receiver architecture with the feedback structure in the RF front-end circuit is used to give good immunity against the large transmitter leakage and to suppress leakage. The system design considerations for receiver on NF and IIP3 have been discussed in detail. The RF Front-END contains a power amplifier (PA) in transmit chain and receive front-end with low-noise amplifier, up/down mixer, LP filter and variable-gain amplifier. In the transmitter, a differential PA with a new power combiner is designed and fabricated in a 0.18-μm technology. The chip area is 2.65 mm × 1.35 mm including...