Sharif Digital Repository

According to International Technology Roadmap for Semiconductors (ITRS), before the end of this decade, we will be entering the era of a billion transistors on a single chip. The major threat toward the achievement of billion transistor on a chip is poor scalability of current interconnect infrastructure. With the advent of "Network on Chip (NoC)" various characters and methodologies of traditional networks were hardly considered on-chip. Failure, Power and Area are the major concepts that should be considered when migrating from traditional interconnection networks to NoCs. In this paper we study the effects of faulty links and nodes on power and performance of mesh based NoC, Also several... 

A core mapping method for reconfigurable network-on-chip (NoC) architectures is presented in this paper. In most of the existing methods, mapping is carried out based on the traffic characteristics of a single application. However, several different applications are implemented and integrated in the modern complex system-on-chips which should be considered by mapping methods. In the proposed method, the reconfiguration (which is achieved by embedding programmable switches between routers of a mesh-based NoC) allows us to dynamically change the network topology in order to adapt it with the running application and optimize the power and performance metrics. The presented network architecture...