Sharif Digital Repository

Plug-in electric vehicles (PEVs) are identified as one of the motivating technologies in smart grid era. However, if their highly disruptive impacts on the distribution system are left unaddressed, it may obstruct both smart grid development and PEV adoption. This chapter develops a novel in-home PEV charging control (PCC) algorithm that schedules both the time and level of charging PEVs incorporating customerﾒs desired comfort level. This optimization-based problem attempts to achieve a trade-off between minimizing the electricity payment and minimizing the waiting time to fully charge the PEVs in presence of a time of use (TOU) pricing tariff combined with inclining block rates (IBRs). The... 

Recently small satellites are used more commonly because of the low launching cost and development of microelectronics. Also lower weight, size, cost and the power consumption of magnetorquer, has made the application of them in controlling attitude of the satellites common. Intensive changes and non-ability of geomagnetic field are some of the problems, which have limited the efficiency of magnetorquers. In this paper a new control method is presented that keeps the attitude of satellite in desired condition only by electromagnetic coils. The distinction of this method is its abilities in comparison with other methods. In this analytic method a direct relation between design parameters,... 

The present work developed a mixed-mode cohesive zone model (CZM) with a mode I failure criterion to predict the delamination bending loads of multilayer, composite printed circuit boards (PCBs) assembled with soldered ball grid array (BGA) components that were reinforced with an underfill epoxy adhesive. Two different delamination modes were observed in these microelectronic assemblies: delamination at the interface between the solder mask and the first conducting layer of the PCB, and PCB subsurface delamination at the interface between the epoxy and glass fibers of one of the prepreg layers. The cohesive parameters for each of the two crack paths were obtained from fracture tests of... 

The present work developed a mixed-mode cohesive zone model (CZM) with a mode I failure criterion to predict the delamination bending loads of multilayer, composite printed circuit boards (PCBs) assembled with soldered ball grid array (BGA) components that were reinforced with an underfill epoxy adhesive. Two different delamination modes were observed in these microelectronic assemblies: delamination at the interface between the solder mask and the first conducting layer of the PCB, and PCB subsurface delamination at the interface between the epoxy and glass fibers of one of the prepreg layers. The cohesive parameters for each of the two crack paths were obtained from fracture tests of... 

A new structure of Capacitive Digital to Analog Converters (CDAC) for SAR ADCs is presented. In this structure, a number of capacitors are used in different series configurations to generate desirable voltage levels based on an input binary code. the proposed CDAC consumes a certain amount of power regardless of the input code. This method achieves more than 99.9% power reduction and 98.9% area reduction compared to the conventional binary weighted CDAC. © 2017 IEEE  

Error propagation analysis is one of the main objectives of fault injection experiments. This analysis helps designers to detect design mistakes and to provide effective mechanisms for fault tolerant systems. However, error propagation analysis requires that the chosen fault injection technique provides a high degree of observability (i.e., the ability to observe the internal values and events of a circuit after a fault is injected). Simulation-based fault injection provides a high observability adequate for error propagation analysis. However, the performance of the simulation-based technique is inadequate to handle today's hardware complexity. As an alternative, FPGA-based fault injection... 

In this paper, an infrastructure for debug of complex SoCs that employs assertions is introduced. The proposed infrastructure combines traditional off-chip analysis techniques with on-chip at-speed debug facilities. The main part of on-chip debug hardware consists of data and transaction monitors. The monitor hardware is automatically generated by synthesizing the assertions that were used for verification and validation before manufacturing. We have integrated the proposed method in a system-level design methodology. By synthesizing various assertions from different kinds in a case study we have studied the overhead of our method. © 2007 IEEE  

Present investigation analyzes the issue of entropy generation in a uniformly heated microchannel heat sink (MCHS). Analytical approach used to solve forced convection problem across MCHS, is porous medium model based on modified Darcy equation for fluid flow and two-equation model for heat transfer between solid and fluid phases. Furthermore, closed form solution of velocity distribution is employed to capture z-direction velocity gradient of flow, which plays a salient role on entropy generation through fluid flow. Analytical expressions for total and thermal entropy generation number (stems from heat transfer), and Bejan number are derived and cast into dimensionless form using velocity... 

In this work, we present a theoretical investigation of the thermal conductivity of hydrogen-passivated graphene antidot lattices. Using a fourth nearest-neighbor force constant method, we evaluate the phonon dispersion of hydrogen-passivated graphene antidot lattices with circular, hexagonal, rectangular and triangular shapes. Ballistic transport models are used to evaluate the thermal conductivity. The calculations indicate that the thermal conductivity of hydrogen-passivated graphene antidot lattices can be one fourth of that of a pristine graphene sheet. This reduction is stronger for right-triangular and iso-triangular antidots among others, all with the same area, due to longer... 

The increasing rate of transient faults necessitates the use of on-chip fault-tolerant techniques in embedded microprocessors. Performance overhead is a challenging problem in on-chip fault-tolerant techniques used in the random logic of the embedded microprocessors. This paper presents a signature-based error detection and roll-back recovery technique for the control logic with much lower performance overhead as compared to many previous techniques. The low performance overhead is achieved by eliminating the fault masking overhead cycles in the previous techniques. The performance overhead is analytically studied, and the analytical results recommend at which fault rate the use of the... 

In this paper, we present an assertion-based verification methodology for system-level design. Transactionlevel concepts are integrated with an assertion language to introduce a useful, effective and familiar assertion description language. Our assertion verification language is capable of specifying system-level assertions for validating performance as well as functional properties. Proper-ties can be verified using offline simulation trace analysis. C++ trace checkers are automatically generated to validate particular simulation runs or to analyze their performance characteristic(s). Using a JPEG decoder as a case study, we demonstrate that the assertion-based verification is highly useful... 

The field-emission properties of molybdenum oxide nanowires grown on a silicon substrate and its emission performance in various vacuum gaps are reported in this article. A new kind of molybdenum oxides named nanowires with nanoscale protrusions on their surfaces were grown by thermal vapor deposition with a length of ~1 μm and an average diameter of ~50 nm. The morphology, structure, composition and chemical states of the prepared nanostructures were characterized by scanning electron microscopy (SEM), high-resolution transmission electron microscopy (HRTEM), X-ray diffraction (XRD) and X-ray photoelectron spectroscopy (XPS). According to XRD, XPS, and TEM analyses, the synthesized samples... 

With the continual scaling of feature size, system failure due to soft errors is getting more frequent in CMOS technology. Soft errors have particularly severe effects in static random-access memory (SRAM)-based reconfigurable devices (SRDs) since an error in SRD configuration bits can permanently change the functionality of the system. Since interconnect resources are the dominant contributor to the overall configuration memory upsets in SRD-based designs, the system failure rate can be significantly reduced by mitigating soft errors in routing fabric. This paper first presents a comprehensive analysis of SRD switch box susceptibility to short and open faults. Based on this analysis, we... 

In this paper, a general Checkpointing technique for rollback error recovery for embedded systems is proposed and evaluated. This technique is independent of used processor and employs the most important feature in control flow error detection mechanisms to simplify checkpoint selection and to minimize the overall code overhead. In this way, during the implementation of a control flow checking mechanism, the checkpoints are added to the program. To evaluate the Checkpointing technique, a pre-processor is implemented that selects and adds the checkpoints to three workload programs running in an 8051 microcontroller -based system. The evaluation is based on 3000 experiments for each... 

This paper presents an experimental evaluation of the effectiveness of three hardware-based control flow checking mechanisms, using software-implemented fault injection (SWIFI) method. The fault detection technique uses reconfigurable of the shelf FPGAs to concurrently check the execution flow of the target program. The technique assigns signatures to the target program in the compile time and verifies the signatures using a FPGA as a watchdog processor to detect possible violation caused by the transient faults. A total of 3000 faults were injected in the experimental embedded system, which is based on an 8051 microcontroller, to measure the error detection coverage. The experimental... 

Purpose: This paper aims to study the thermal and thermo-hydraulic performances of ferro-nanofluid flow in a three-dimensional trapezoidal microchannel heat sink (TMCHS) under uniform heat flux and magnetic fields. Design/methodology/approach: To investigate the effect of direction of Lorentz force the magnetic field has been applied: transversely in the x direction (Case I);transversely in the y direction (Case II); and parallel in the z direction (Case III). The three-dimensional governing equations with the associated boundary conditions for ferro-nanofluid flow and heat transfer have been solved by using an element-based finite volume method. The coupled algorithm has been used to solve... 

In the recent decades, cleanrooms have found growing applications in broad range of industries such as pharmacy and microelectronics. Concerns about negative effects of the contaminant exposure on the human health and product quality motivate many researchers towards understanding of the airflow and contaminant distribution though these environments. With an improvement in computational capacity of the computers, computational fluid dynamics (CFD) technique has become a powerful tool to study the engineering problems including indoor air quality (IAQ). In this research, indoor airflow in a full-scale cleanroom is investigated numerically using Eulerian-Eulerian approach. To evaluate the... 

This paper reports transistor-level design of a new continuous-time (CT), discrete-time (DT) cascaded sigma delta modulator (SDM). The combination of a CT first stage and a DT second stage was utilized to realize a high speed, high resolution analog-to-digital converter (ADC). Power consumption of CT first stage is lowered by optimizing the gain coefficients of CT integrators in a feedforward topology. Moreover double sampling (CDS) was used in second stage integrators to further reduce power consumption. Proposed new SDM is simulated in 0.18μm CMOS technology and achieves 84dB dynamic range for a 10MHz signal bandwidth. Total analog power dissipation measured was 44mW  

The field emission properties of MoO2 nanostars grown on a silicon substrate and their emission performance in various vacuum gaps are reported in this article. A new structure of molybdenum oxides, named a nanostar, is grown by thermal vapor deposition with a length of ̃1 μm, a thickness of ̃50 nm, and its width in the range of 500-700 nm. The morphology, structure, composition, and chemical states of the prepared nanostars were characterized by scanning electron microscopy, high-resolution transmission electron microscopy, X-ray diffraction (XRD), and X-ray photoelectron spectroscopy (XPS). According to XRD analysis, the grown nanostructures are composed of both crystalline Mo4O11 and...