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A Micro-FT-UART for safety-critical SoC-based applications
, Article International Conference on Availability, Reliability and Security, ARES 2009, Fukuoka, Fukuoka Prefecture, 16 March 2009 through 19 March 2009 ; 2009 , Pages 316-321 ; 9780769535647 (ISBN) ; Miremadi, S. G ; Ejlali, A. I ; Sharif University of Technology
2009
Abstract
This paper presents the design of a fault-tolerant universal asynchronous receiver transmitter (UART) called micro-FT-UART for safety-critical SoC-based applications. This UART exploits advantages of three fault-tolerant techniques to tolerate soft errors. The three techniques are triple modular redundancy (TMR), Hamming code and a new technique called correction by parity storing (CPS). An VHDL model of a micro-UART is simulated by the ModelSim v.6.0 and synthesized by the Synopsys Design Compiler v.X-2005.09- SP2. About 1000 single-bit errors and 1000 multiple-bit errors are injected into different parts of the micro-UART to find out the error sensitivity of each specific part. Considering...
High-level modeling approach for analyzing the effects of traffic models on power and throughput in mesh-based NoCs
, Article Proceedings of the IEEE International Frequency Control Symposium and Exposition, 4 January 2008 through 8 January 2008, Hyderabad ; 2008 , Pages 415-420 ; 0769530834 (ISBN); 9780769530833 (ISBN) ; Mirza Aghatabar, M ; Hessabi, S ; Pedram, M ; VLSI Society of India ; Sharif University of Technology
2008
Abstract
Traffic models exert different message flows in a network and have a considerable effect on power consumption through different applications. So a good power analysis should consider traffic models. In this paper we present power and throughput models in terms of traffic rate parameters for the most popular traffic models, i.e. Uniform, Local, HotSpot and First Matrix Transpose (FMT) as a permutational traffic model. We also select Mesh topology as the most prominent NoC topology and validate the presented models by comparing our results against simulation results from Synopsys Power Compiler and Modelsim From the comparison, we show that our modeling approach leads to average error of 2%...
An FPGA based implementation of G.729
, Article IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, 23 May 2005 through 26 May 2005 ; 2005 , Pages 3571-3574 ; 02714310 (ISSN) ; Vahdat, B ; Radfar, M. H ; Sharif University of Technology
2005
Abstract
Main objective of this article is to present the implementation and simulation of a Conjugate Structure Algebraic Code Excited Linear Prediction speech coder (CSACELP) based upon ITU-T's G.729 recommendation and to optimize it for real-time implementation on an FPGA. The suggested architecture is characterized by pipelining and parallel operation of functional units; using fixed point two's complement representation for integers. The design was functionally verified by utilizing the ModelSim software package from Mentor Graphics Corporation Company and then synthesized by Xilinx Integrated Software Environment (ISE) 6.1 software. Preliminary results show that the overall system delay is less...