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    High-throughput low-complexity systolic montgomery multiplication over GF(2m) Based on Trinomials

    , Article IEEE Transactions on Circuits and Systems II: Express Briefs ; Volume 62, Issue 4 , January , 2015 , Pages 377-381 ; 15497747 (ISSN) Bayat Sarmadi, S ; Farmani, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    Cryptographic computation exploits finite field arithmetic and, in particular, multiplication. Lightweight and fast implementations of such arithmetic are necessary for many sensitive applications. This brief proposed a low-complexity systolic Montgomery multiplication over GF(2m). Our complexity analysis shows that the area complexity of the proposed architecture is reduced compared with the previous work. This has also been confirmed through our application-specific integrated circuit area and time equivalent estimations and implementations. Hence, the proposed architecture appears to be very well suited for high-throughput low-complexity cryptographic applications  

    Isogeny diffie-hellman and key encapsulation using a customized pipelined montgomery multiplier

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; 2021 ; 15498328 (ISSN) Farzam, S. M. H ; Bayat-Sarmadi, S ; Mosanaei-Boorani, H ; Alivand, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2021
    Abstract
    We present a pipelined Montgomery multiplier tailored for SIKE primes. The latency of this multiplier is far shorter than that of the previous work while its frequency competes with the highest-rated ones. The implementation results on a Virtex-7 FPGA show that this multiplier improves the time, the area-time product (AT), and the throughput of computing modular multiplication by at least 2.30, 1.60, and 1.36 times over SIKE primes respectively. We have also developed a CPU-like architecture to perform SIDH and SIKE using several instances of our modular multiplier. Using four multipliers on a Virtex-7 FPGA, the encapsulation and the decapsulation of SIKE can be performed at least 1.45 times... 

    Fast supersingular isogeny diffie-hellman and key encapsulation using a customized pipelined montgomery multiplier

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 69, Issue 3 , 2022 , Pages 1221-1230 ; 15498328 (ISSN) Farzam, S. M. H ; Bayat Sarmadi, S ; Mosanaei Boorani, H ; Alivand, A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2022
    Abstract
    We present a pipelined Montgomery multiplier tailored for SIKE primes. The latency of this multiplier is far shorter than that of the previous work while its frequency competes with the highest-rated ones. The implementation results on a Virtex-7 FPGA show that this multiplier improves the time, the area-time product (AT), and the throughput of computing modular multiplication by at least 2.30, 1.60, and 1.36 times over SIKE primes respectively. We have also developed a CPU-like architecture to perform SIDH and SIKE using several instances of our modular multiplier. Using four multipliers on a Virtex-7 FPGA, the encapsulation and the decapsulation of SIKE can be performed at least 1.45 times... 

    High-Performance Architecture for Post-Quantum Cryptography Based on Elliptic Curve Isogeny

    , Ph.D. Dissertation Sharif University of Technology Farzam, Mohammad Hossein (Author) ; Bayat Sarmadi, Siavash (Supervisor)
    Abstract
    Public-key cryptography is vital to secure digital communication. The classic instances of these cryptosystems are insecure against large-scale quantum computers. As a result, post-quantum cryptography has emerged as a replacement, which includes different categories. Isogeny-based schemes are one of the promising candidates mainly because of their smaller public key length. Due to high computational cost of such schemes, efficient implementations are significantly important. In this thesis, we have presented various solutions at three different abstraction layers. At the lowest layer, which deals with modular arithmetic, two hardware architectures are presented to perform modular...