Sharif Digital Repository

An 8-bit High-speed folding/interpolating ADC is presented. Designed in 0.18μm CMOS technology, the ADC dissipates only 50mW from a single 1.5V supply. A novel technique based on using both N and P folding cells is used to widen the input range and a self-calibration technique based on using Trimmable MOSFETs is employed to improve the static and dynamic performance  

Currently, there are no studies investigating the issue of speed optimization of Gain-Boosted Cascode Amplifier in low voltage applications. This is mainly because of the complicated transfer function of high-swing Gain-Boosted Cascode Amplifier structures. This paper proposes a novel and generic model for this amplifier and presents a thorough analysis of its behavior. The aim of this optimization is to eliminate the well-known slow timing component in the step response and obtain the minimum achievable settling time. An ultra high-speed amplifier is presented finally  

A novel current reference with low temperature and supply sensitivity and without any external component has been developed in a 0.25 μm mixed-mode process. The circuit is based on a bandgap reference (BGR) voltage and a CMOS circuit similar to a beta multiplier. An NMOS transistor in triode region has been used in place of a resistor in conventional beta multiplier to achieve a current which has a negative temperature coefficient and only oxide thickness dependent. The BGR voltage has a positive temperature coefficient to cancel the negative temperature coefficient of the beta multiplier. The simulation results using Bsim3v3 model show max-to-min fluctuation of less than 1 % over a... 

A single 1.5 V supply, second order band-pass gm-C filter based on a low-voltage transconductor architecture in standard 0.6 um CMOS process is presented. A dc level shifter circuit (DCLS) is utilized at the input of the proposed transconductor to increase the dc level of the input signal. This makes the input transistors operate in the desired region and hence input voltage swing enhances. DCLS uses a simple voltage doubler as its supply while other parts of the circuit use the main 1.5 V supply. Proposed transconductor shows a THD of -60 dB for 1.4 Vpp,diff input signal with 1 MHz frequency. Also a proper common-mode detector circuit is developed for this low-voltage application. The... 

Decreasing Drain-Induced-Barrier-Lowering (DIBL) is one of the nondesirable short-channel effects, causes the threshold voltage of the transistor to be reduced by increasing the drain voltage. DIBL makes it impossible for engineers to consider VT as a constant, and it is necessary to calculate VT as a function of the drain voltage. Therefore, to consider the DIBL effect in the design of ICs, a large computational burden is imposed on the system, which slows down the simulation process in circuit-level simulators. Accordingly, a Nonlinear Feed-Forward Memory-Less (NFFML) model using the Gram-Schmidt orthogonalization approach is proposed, which calculates the VT of the new generation of... 

Based on transport and magnetic measurements on Gd(Ba2-xPr x)Cu3O7+δ, and some other properties of high temperature superconductors (HTSC), we have extracted similarities between superconductors, two-dimensional electron gas (2D-EG) i.e., MOSFETs. These are based on properties such as superconductor-insulator transition in superconductors and metal-insulator transition (MIT) in 2D-EG with doping and magnetic field, localization in transport conduction, quantum unit of resistance at MIT, larger change in resistivity from critical doping to the insulating side in comparison with change from critical doping to the metallic side, and strongly electron-electron coupling. These similarities could... 

Nowadays power electronic devices have a wide usage in the industries and different electrical equipment for power conditioning. As a point of view, reliability is one of important figure of merits that should be considered to have long life time and also have more probability to do exactly the proposed mission. In this paper some methods are presented to improve the reliability of power electronic components. Also some methods of system reliability improvement are reviewed. One group of converters is DC-DC step down converter which is used in different applications such as battery charger and voltage regulator. In this paper as an example, reliability of a DC-DC step down converter with... 

This paper gives the design and analysis approaches for the class-E power amplifier with a shunt inductor under the nominal conditions, i.e., zero-current switching (ZCS) and zero-current derivative switching (ZCDS), with taking into account the MOSFET nonlinear output parasitic capacitance at any duty ratio. Although, the class-E ZCS/ZCDS conditions obtained high-efficiency, but the switch-current waveform affected by the slope of the voltage across the MOSFET nonlinear drain-to-source parasitic capacitance during the switch-off state, which restricted the operating frequency. On the other hand, the duty ratio is an adjustment parameter to obtain high-frequency operation. Therefore, the... 

In this paper the electrical characteristics of a novel nanoscale double-gate MOSFET (DG-MOSFET) have been investigate by a full Quantum Mechanical simulation framework. This framework consists of Non-Equilibrium Green's Function (NEGF) solved self-consistently with Poisson's Equation. Quantum transport equations are solved in two-dimension (2-D) by recursive NEGF method in active area of the device to obtain the charge density and Poisson's equation is solved in entire domain of simulation to get potential profile. Once self-consistently achieved all parameters of interest (e.g. potential profile, charge density, DIBL, etc) can be measured. In this novel DG-MOSFET structure, a front gate... 

For the first time, we present self-consistent solution of ultrathin body device structures to investigate the device parameters variation on the characteristics of nanoscale MOSFET. Our two dimensional (2-D) device simulator Is based on Nonequlibrium Green's Function (NEGF) forma lism. Starting from a basic structure (DG-MOSFET) with a gate length of 10 nm, variation of gate length, channel thickness, gate oxide parameters was carried out in connection with the numerical calculation of device characteristics. In this work Quantum transport equations are solved in 2-D by NEGF method in active area of the device to obtain the charge density and Poisson's equation is solved in entire domain of... 

This paper suggests methods for improving efficiency of a high step up high efficiency converter based on three state commutation cells. A loss analysis has been performed to identify the source of power loss. Based on this analysis, methods are presented to reduce losses in the most power dissipating elements. These methods include replacing some power diodes with large conduction losses with MOSFETs having small on-state resistance. Efficiency improvement up to %1.25 percent is verified in simulation and experimental results  

A compact aging model for circuit simulation has been developed by considering all possible trapped carriers within MOSFETs. The hot carrier effect and the N(P)BTI effect are modeled by integrating the substrate current as well as the oxide field change due to the trapped carriers. Additionally, the carriers trapped within the highly resistive drift region are included for high-voltage (HV)-MOSFET modeling. The aging model considers the dynamic trap-density increase as a function of circuit-operation time with dynamically varying stress conditions for each individual MOSFET. A self-consistent solution is obtained by iteratively solving the Poisson equation including the trap density. The... 

The reported investigation aims at developing a compact model for circuit-aging simulation. The model considers dynamic trap-density increase during circuit operation in a consistent way. The model has been applied to an SRAM cell, where it is believed that the NBTI effect dominates. Our simulation verifies that the hot-carrier effect has a compensating influence on the NBTI aging of SRAM cells. © 2017 The Japan Society of Applied Physics  

It is shown that a compact MOSFET-aging model for circuit simulation is possible by considering the dynamic trap-density increase, which is induced during circuit operation. The dynamic trap/detrap phenomenon, which influences the switching performance, is also considered on the basis of well-known previous results. Stress-dependent hot-carrier effect and NBTI effect, origins of the device aging, are modeled during the circuit simulation for each device by integrating the substrate current as well as by determining the oxide-field change due to the trapped carriers over the individual stress-duration periods. A self-consistent solution can be obtained only by iteratively solving the Poisson... 

We have developed a methodology to simulate circuit aging including the device fabrication variation with less simulation effort. As an example a 6T SRAM cell has been investigated. It is demonstrated that the variability range of the circuit performance is further enhanced due to the long-term device aging. Among the device parameters, the impurity concentration variation plays a particularly important role for the circuit performance variation. However, most sensitive for the aging degradation is the channel-length variation, because it increases the aging effect drastically. Further, the individual aging of each MOSFET is strongly dependent on the actual stress during circuit operation. ©... 

In this paper, the large deformation frictional contact of powder forming process is modeled based on a new computational algorithm by imposing the contact constraints and modifying the contact properties of frictional slip. A simple and efficient numerical algorithm is presented for imposing the contact constraints and frictional contact properties based on the node-to-surface contact technique to simulate the large deformation contact problem in the compaction process of powder. The Coulomb friction law is used to simulate the friction between the rigid punch and the workpiece by the use of penalty approach. A double-surface cap plasticity model is employed together with the nonlinear... 

In this paper, the three-dimensional large deformation frictional contact of powder forming process is modeled using a simple computational algorithm based on the augmented-Lagrange approach. The technique is applied by imposing the contact constraints and modifying the contact properties of frictional slip through the node-to-surface (NTS) contact algorithm. The Coulomb friction law is employed to simulate the friction between the rigid punch and the work-piece by the use of penalty and augmented-Lagrange approaches. It is shown that the augmented-Lagrange technique significantly improves imposing of the constraints on contact surfaces. The nonlinear contact friction algorithm is employed... 

In this study, a new LLC resonant converter for high-voltage high-power applications is introduced. The introduced power converter is a two-phase interleaved full-bridge based that uses a transformer with secondary and tertiary windings to obtain higher output voltage. Zero voltage switching (ZVS) at MOSFETs turn on and zero current switching (ZCS) for all the output diodes at turn off are achieved for a wide range of input voltage (100 V-200 V) and output power (200 W-1500 W) variations. Simulation results show a 95% peak efficiency. © 2021 IEEE  

A very low voltage transconductor for video frequency range applications and compatible with standard CMOS technology is described. In the proposed transconductor, except the DC level shifter circuit (DCLS), the whole transconductor uses the main supply voltage [which can be as low as 1.5 V in a standard 0.6 μm CMOS technology] while the DCLS uses a simple charge-pump circuit as its supply voltage and has a very low current consumption. In addition, proper common-mode sense and charge-pump circuits are developed for this low-voltage application. Meanwhile, some techniques to improve the frequency response, linearity, and noise performance of the proposed transconductor are described. In a... 

We have applied Rosenbrock's optimization algorithm to obtain the optimized efficiency of a solar cell and its structural parameters. To obtain these parameters, we have developed a computer program for simultaneous optimization and simulation of the solar cell. We have used experimental data on the electrical and optical properties of a-Si1-xCx layers, put them into the written code and obtained the optimized parameters of this solar cell. The maximum efficiency is 6.32% which is close to one experimental result. © 2004 Elsevier B.V. All rights reserved