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    Interference neutralization using lattice codes

    , Article 2013 IEEE Information Theory Workshop, ITW 2013 2013 ; 2013 ; 9781479913237 (ISBN) Ghasemi Goojani, S ; Behroozi, H ; Sharif University of Technology
    2013
    Abstract
    Deterministic approach of [1] models the interaction between the bits that are received at the same signal level by the modulo 2 sum of the bits where the carry-overs that would happen with real addition are ignored. By this model in a multi-user setting, the receiver can distinguish most significant bits (MSBs) of the stronger user without any noise. A faithful implementation of the deterministic model requires one to 'neutralize interference' from previous carry over digits. This paper proposes a new implementation of 'interference neutralization' [2] using structured lattice codes. We first present our implementation strategy and then, as an application, apply this strategy to a symmetric... 

    Operand Width Aware Hardware Reuse: A low cost fault-tolerant approach to ALU design in embedded processors

    , Article Microelectronics Reliability ; Volume 51, Issue 12 , December , 2011 , Pages 2374-2387 ; 00262714 (ISSN) Fazeli, M ; Namazi, A ; Miremadi, S. G ; Haghdoost, A ; Sharif University of Technology
    2011
    Abstract
    This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is motivated by two facts: (1) Many of the produced and consumed values are narrow-width values in the embedded processors, i.e. they have leading zeros or ones in their most significant bits. This indicates that only a fraction of the circuit is performing useful operations when a particular arithmetic or logic circuit in the ALU is operating on narrow-width values; (2) other circuits of the ALU are not used, when a particular arithmetic or logic circuit is being utilized to perform a specific operation in the ALU in the... 

    Reliable and energy efficient MLC STT-RAM buffer for CNN accelerators

    , Article Computers and Electrical Engineering ; Volume 86 , 2020 Jasemi, M ; Hessabi, S ; Bagherzadeh, N ; Sharif University of Technology
    Elsevier Ltd  2020
    Abstract
    We propose a lightweight scheme where the formation of a data block is changed in such a way that it can tolerate soft errors significantly better than the baseline. The key insight behind our work is that CNN weights are normalized between -1 and 1 after each convolutional layer, and this leaves one bit unused in half-precision floating-point representation. By taking advantage of the unused bit, we create a backup for the most significant bit to protect it against the soft errors. Also, considering the fact that in MLC STT-RAMs the cost of memory operations (read and write), and reliability of a cell are content-dependent (some patterns take larger current and longer time, while they are...