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    Multi-period lot sizing and job shop scheduling with compressible process times for multilevel product structures

    , Article International Journal of Production Research ; Volume 51, Issue 20 , 2013 , Pages 6229-6246 ; 00207543 (ISSN) Karimi Nasab, M ; Seyedhoseini, S. M ; Modarres, M ; Heidari, M ; Sharif University of Technology
    2013
    Abstract
    This paper presents mathematical modelling of joint lot sizing and scheduling problem in job shop environment under a set of working conditions. The main feature of the problem is to deal with flexible machines able to change their working speeds, known as process compressibility. Furthermore, produced items should be assembled together to make final products. In other words, the products have a multilevel structure, shown with bill of materials. As the problem is proved to be strongly NP-hard, it is solved by a memetic algorithm here. Computational experiences on the data of Mega Motor company are reported. Also, further experiences on random test data confirm the performance of the... 

    Using intra-line level pairing for graceful degradation support in PCMs

    , Article Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, 8 July 2015 through 10 July 2015 ; Volume 07-10-July-2015 , 2015 , Pages 527-532 ; 21593469 (ISSN) ; 9781479987184 (ISBN) Asadinia, M ; Sarbazi Azad, H ; Sharif University of Technology
    IEEE Computer Society  2015
    Abstract
    In Phase-Change Memory (PCM), the number of writes a cell can take before wearing-out is limited and highly varied due to unbalanced write traffic and process variation. After the failure of weak cells and in presence of large number of failed lines, some techniques have been proposed to further prolong the lifetime of a PCM device by remapping failed lines to spares and salvage a PCM device with graceful degradation. Others rely on handling failures through inter-line pairing. Observations reveal that most of cells in a line are healthy when the line is marked as faulty by any of these proposals. To overcome this deficiency, we propose Intra-line Level Pairing(ILP), a technique that... 

    Wind energy status of Iran: Evaluating Iran's technological capability in manufacturing wind turbines

    , Article Renewable and Sustainable Energy Reviews ; Volume 15, Issue 8 , 2011 , Pages 4200-4211 ; 13640321 (ISSN) Bagheri Moghaddam, N ; Mousavi, S. M ; Nasiri, M ; Moallemi, E. A ; Yousefdehi, H ; Sharif University of Technology
    Abstract
    Iran, as a developing country, will be confronted with a significant increase in electricity demand in future years. Being a petroleum producing country has resulted in extreme subsidies for energy production from fossilized resources such as oil and gas. This issue is one of the most important factors regarding underdevelopment of renewable energies in Iran. Expansive use of fossil resources in providing the necessary energy has resulted in Iran being among the 20 countries that have a share in the 75% spread of greenhouse gases. This issue has resulted in greater attention on behalf of the energy sectors policy makers regarding renewable energies, especially wind. Awareness regarding the... 

    Handling hard errors in PCMs by using intra-line level schemes

    , Article Advances in Computers ; Volume 118 , 2020 , Pages 79-109 Asadinia, M ; Sarbazi Azad, H ; Sharif University of Technology
    Academic Press Inc  2020
    Abstract
    In this chapter, we first introduce one shifting mechanisms in order to further prolonging the lifetime of a phase change memory (PCM) device, reducing the write rate to PCM cells, and handling cell failures when hard faults occur. In this line, Byte-level Shifting Scheme (BLESS) is addressed and reduces write pressure over hot cells of blocks. Additionally, we illustrate that using the MLC capability of PCM and manipulating the data block to recover faulty cells can also be used for error recovery purpose. Next, we propose another intra-line level pairing scheme (ILP). This novel recovery mechanism can statically partition a data block into a small number of groups and efficiently benefits... 

    Inter-line level schemes for handling hard errors in PCMs

    , Article Advances in Computers ; Volume 118 , 2020 , Pages 49-78 Asadinia, M ; Sarbazi Azad, H ; Sharif University of Technology
    Academic Press Inc  2020
    Abstract
    To address the problem of fast degradation in PCM main memory systems in the presence of severe cell wear-out, this chapter introduces and evaluates some ways to deal with hard error issues in phase change memory. Our observation reveals when some memory pages reach their endurance limits, other pages may be far from their limits even when using a perfect wear-leveling. Recent studies have proposed redirection or correction schemes to alleviate this problem, but all suffer from poor throughput or latency. In this chapter, we also propose On-demand page paired PCM (OD3P) memory system. Our technique mitigates the problem of fast failure of pages by redirecting them onto other healthy pages,... 

    After-sales Service Pricing in a Two-echelon Supply Chain

    , M.Sc. Thesis Sharif University of Technology Ghayouri Pirsolton, Sepideh (Author) ; Najafi, Mehdi (Supervisor)
    Abstract
    The present study proposes a pricing model for manufacturing and customer support companies which is carried out in the form of multi-level programming. In this model, the manufacturer is considered as the leader and supporting companies as followers. In fact, manufacturer sets up the price level for its customer support first and then according to this price level, customer support companies choose their products and specify the level of after-sales services and the prices. The purpose of this study is to provide insight into the analysis of the after-sales services in a supply chain. The results can be notable for managers in order to demonstrate the impact of different strategies of... 

    Multi-level authorisation model and framework for distributed semantic-aware environments

    , Article IET Information Security ; Volume 4, Issue 4 , 2010 , Pages 301-321 ; 17518709 (ISSN) Amini, M ; Jalili, R ; Sharif University of Technology
    Abstract
    Semantic technology is widely used in distributed computational environments to increase interoperability and machine readability of information through giving semantics to the underlying information and resources. Semantic-awareness, distribution and interoperability of new generation of distributed systems demand an authorisation model and framework that satisfies essential authorisation requirements of such environments. In this study, the authors propose an authorisation model and framework based on multi-security-domain architecture for distributed semantic-aware environments. The proposed framework is founded based on the MA(DL)2 logic, which enables policy specification and inference... 

    Fast fault detection method for modular multilevel converter semiconductor power switches

    , Article IET Power Electronics ; Volume 9, Issue 2 , 2016 , Pages 165-174 ; 17554535 (ISSN) Haghnazari, S ; Khodabandeh, M ; Zolghadri, M. R ; Sharif University of Technology
    Institution of Engineering and Technology  2016
    Abstract
    This study proposes a new fault detection method for modular multilevel converter (MMC) semiconductor power switches. While in common MMCs, the cells capacitor voltages are measured directly for control purposes, in this study voltage measurement point changes to the cell output terminal improving fault diagnosis ability. Based on this measurement reconfiguration, a novel fault detection algorithm is designed for MMCs semiconductor power switches. The open circuit and short circuit faults are detected based on unconformity between modules output voltage and switching signals. Simulation and experimental results confirm accurate and fast operation of the proposed method in faulty cell... 

    An optimal integrated lot sizing policy of inventory in a bi-objective multi-level supply chain with stochastic constraints and imperfect products

    , Article Journal of Industrial and Production Engineering ; Volume 35, Issue 1 , 2018 , Pages 6-20 ; 21681015 (ISSN) Gharaei, A ; Pasandideh, S. H. R ; Akhavan Niaki, S. T ; Sharif University of Technology
    Taylor and Francis Ltd  2018
    Abstract
    This paper provides a developed mathematical model to derive the optimal integrated lot sizing in a multi-level supply chain with imperfect quality products. The developed mathematical model has a bi-objective function, with conflicting goals, minimizing the chain inventory costs and maximizing the chain total profit aided to find optimum policy for integrated lot sizing. We further actualize the problem by assuming multiple stochastic constraints. The mathematical formulation of the problem is stochastic, nonlinear, and large. In this regard, the interior point algorithm that is developed as more effective algorithm with less iteration is used for solving the recent convex nonlinear model.... 

    On optimal dynamic pegging in rescheduling for new order arrival

    , Article Computers and Industrial Engineering ; Volume 136 , 2019 , Pages 46-56 ; 03608352 (ISSN) Moghaddam, S. K ; Saitou, K ; Sharif University of Technology
    Elsevier Ltd  2019
    Abstract
    A rescheduling method for new order arrival is presented based on the concept of dynamic pegging in multi-level production. Upon the arrival of new, unplanned orders, dynamic pegging enables the re-assignment of the Work-In-Progress (WIP) to the existing or newly arrived orders in such a way that the cost of rescheduling is minimized. A simple yet inspiring Mixed Integer Programming (MIP) model is proposed that combines dynamic pegging with rescheduling. The resulting schedules are compared with the ones obtained from two other basic rescheduling approaches. Analysis of the comparisons confirm the superiority of the proposed method in terms of total rescheduling costs. © 2019  

    Mental arousal level recognition competition on the shared database

    , Article 27th Iranian Conference on Electrical Engineering, ICEE 2019, 30 April 2019 through 2 May 2019 ; 2019 , Pages 1730-1736 ; 9781728115085 (ISBN) Saidi, M ; Rezania, S ; Khazaei, E ; Taghibeyglou, B ; Hashemi, S. S ; Kaveh, R ; Abootalebi, V ; Bagheri, S ; Homayounfar, M ; Asadi, M ; Mohammadian, A ; Mozafari, M ; Hasanzadeh, N ; DIni, H ; Sarvi, H. M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    This paper presents the results of the shared task with the aim of arousal level recognition for the competition held in conjunction with the 27th Iranian Conference on Electrical Engineering (ICEE 2019). A database annotated with arousal level labels released by Research Center for Development of Advanced Technologies. The contest was held on arousal database according to a defined protocol. Three teams were able to enter into the final stage of the competition according to compare their performance measure with the baseline method. The baseline method is proposed by the data owner. The aim of this paper is outlining the database, protocol design, and providing an overview of top-ranked... 

    Addressing issues with MLC phase-change memory

    , Article Advances in Computers ; Volume 118 , 2020 , Pages 111-133 Asadinia, M ; Sarbazi Azad, H ; Sharif University of Technology
    Academic Press Inc  2020
    Abstract
    All of the presented solutions in this book focused on using MLC phase change memory (PCM) due to density advantage and prolonging PCM lifetime. However, resistance drift can be one of the challenging issues for MLC PCMs. While it is desired to have the density advantage of MLC, the trade-off is resistance drift. Since MLCs have closely separated resistance regions, drift has a chance of overlapping intermediate regions. It may then bring out either single bit or multi-bit soft error. Indeed, drift source is related to the semi amorphous resistance regions that are metastable vs time and temperature while crystalline resistance proves to be stable across time and temperature. This chapter... 

    The emerging phase change memory

    , Article Advances in Computers ; Volume 118 , 2020 , Pages 15-28 Asadinia, M ; Sarbazi Azad, H ; Sharif University of Technology
    Academic Press Inc  2020
    Abstract
    This chapter evaluates viewpoints on the Phase Change Memory (PCM) devices and materials entailing multi-level cell (MLC) phase change memory as well as its trade-offs. This chapter lists the main difficulties related to PCMs and possible recommendations to address those challenges. The next chapters introduce some simple techniques to alleviate some of the problems listed here. © 2020 Elsevier Inc  

    Enhancing reliability of emerging memory technology for machine learning accelerators

    , Article IEEE Transactions on Emerging Topics in Computing ; Volume 9, Issue 4 , April , 2021 , Pages 2234-2240 ; 21686750 (ISSN) Jasemi, M ; Hessabi, S ; Bagherzadeh, N ; Sharif University of Technology
    IEEE Computer Society  2021
    Abstract
    An efficient and reliable Multi-Level Cell (MLC) Spin-Transfer Torque Random Access Memory (STT-RAM) is proposed based on a Drop-And-Rearrange Approach, called DARA. Since CNN models are rather robust, less important bits are dropped, allowing important bits to be written in safe and reliable Single-Level Cell mode. Also, bits are rearranged to make the representation better aligned with memory cell characteristics. Bits with higher impact on the features value are stored in safer bit positions reducing the chance of read/write circuits to malfunction. Experimental results show that our approach provides comparable to error-free scenario reliability level, while doubling the bandwidth and... 

    Multi-level decomposition approach for problem solving and design in software engineering

    , Article Proceedings of the Annual Southeast Conference, 24 March 2011 through 26 March 2011 ; March , 2011 , Pages 249-254 ; 9781450306867 (ISBN) Najafi, A ; Niu, N ; Najafi, F ; Sharif University of Technology
    2011
    Abstract
    In general, decomposition methods can facilitate the process of solving sophisticated and heterogonous problems in the area of software development and engineering. These approaches are assisting to decompose problems based on different disciplines, characteristics and functionalities that is results into increasing the computational efficiency (e.g. parallel processing/computing) and accelerate the software changing process, software modifications and error tracking. Essentially, these approaches contribute to the degree of modularity to decompose a complex problem into different sub-problems and to focus on local objectives. There are different approaches that are used to decompose a... 

    STAIR: high reliable STT-MRAM aware multi-level I/O cache architecture by adaptive ECC allocation

    , Article 2020 Design, Automation and Test in Europe Conference and Exhibition, DATE 2020, 9 March 2020 through 13 March 2020 ; 2020 , Pages 1484-1489 Hadizadeh, M ; Cheshmikhani, E ; Asadi, H ; ACM Special Interest Group on Design Automation (SIGDA); et al.; European Design and Automation Association (EDAA); European Electronic Chips and Systems Design Initiative (ECSI); IEEE Council on Electronic Design Automation (CEDA); SEMI Strategic Technology Community and Electronic System Design Alliance (ESD Alliance) ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2020
    Abstract
    Hybrid Multi-Level Cache Architectures (HCAs) are promising solutions for the growing need of high-performance and cost-efficient data storage systems. HCAs employ a high endurable memory as the first-level cache and a Solid-State Drive (SSD) as the second-level cache. Spin-Transfer Torque Magnetic RAM (STT-MRAM) is one of the most promising candidates for the first-level cache of HCAs because of its high endurance and DRAM-comparable performance along with non-volatility. However, STT-MRAM faces with three major reliability challenges named Read Disturbance, Write Failure, and Retention Failure. To provide a reliable HCA, the reliability challenges of STT-MRAM should be carefully addressed.... 

    Improving Write Efficiency in MLC PCM Memory

    , M.Sc. Thesis Sharif University of Technology Rashidi, Saeed (Author) ; Sarbazi-Azad, Hamid (Supervisor)
    Abstract
    With increasing number of cores and developing sophisticated applications in today’s computer systems, larger main memory capacity is increasingly demanded. Unfortunately, DRAM cannot satisfy the increasing demand for larger main memory capacity due to its power and scalability limits that makes further scaling of DRAM infeasible. Phase Change Memory (PCM) is one of the most promising candidates to be used at main memory level of the memory hierarchy because it is more scalable, denser, and consumes less standby power compared to DRAM. PCM is a new resistive memory which is capable of storing data based on resistance values. The wide resistance range of PCM allows for storing multiple bits... 

    Integrated Road Reopening and Disaster Relief Programming: Problem Formulation and Solution Procedure

    , M.Sc. Thesis Sharif University of Technology Dabiri, Sina (Author) ; Poorzahedy, Hossain (Supervisor)
    Abstract
    This research deals with the joint problem of reopening the roads closed after a disastrous natural event and the damaged area relief programming. While these two problems are connected to each other by the joint resources of ruins and debris removal, they are usually treated separately in the literature, and their solutions are sought in practice by the art of experienced authorities. This study formulates a dynamic tri-level integer programming problem to represent the two problems of Road Reopening and Relief, in which the crisis manager has the objective of minimizing the death tolls over a planning time interval. It identifies the roads for reopening at the first level; and the second... 

    Multi Level and Multi Products Location-routing Problem for Perishable Foods under Uncertainties

    , M.Sc. Thesis Sharif University of Technology Agha Mohammad Ghasem, Maryam (Author) ; Rafee, Majid (Supervisor)
    Abstract
    Distribution is a necessary part of a supply chain. Location-routing problem is a problem that decide about location of facility , allocation and routing for vehicle. This research focus on modeling for multi-level and multi-product for perishable foods that include five suppliers, three plants, two depots and ten costumers. costumers and products classify according to their importance for the company and their quality into three batch. In order to decreasing of cost return orders and damaged products, a special system are Designed that products can be sent again. In real world we do not have any certain data for model’ parameters, then we consider uncertainty and use robust for showing... 

    A High-Performance and Power-Efficient Design of Memory Hierarchy in Multi-Core Systems Using Non-Volatile Technologies

    , Ph.D. Dissertation Sharif University of Technology Arjomand, Mohammad (Author) ; Sarbazi-Azad, Hamid (Supervisor)
    Abstract
    Ever increasing number of on-chip processors coupled with the trend towards rising memory footprints of the programs increases the demand for larger cache and main memory to hide the long latency of disk system. During the last three decades, SRAM- and DRAM-based memory successfully kept pace with this capacity demand by exponential reduction in cost per bit. Feedbacks from industry also confirms that entering sub-20nm technology era with dominant role of leakage power, however, SRAM and DRAM memories are confronting serious scalability and power limitations. To this end, researchers always pursuit some circuit-level and architectural proposals for incorporating non-volatile technologies in...