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This paper considers scheduling tasks while minimizing the power consumption of one or more processors, each of which can go to sleep at a fixed cost α. There are two natural versions of this problem, both considered extensively in recent work: minimize the total power consumption (including computation time), or minimize the number of "gaps" in execution. For both versions in a multiprocessor system, we develop a polynomial-time algorithm based on sophisticated dynamic programming. In a generalization of the power-saving problem, where each task can execute in any of a specified set of time intervals, we develop a (1+23α) -approximation, and show that dependence on α is necessary. In... 

Multiprocessor systems have been widely used for the execution of parallel applications. Task scheduling is crucial for the right operation of multiprocessor systems, where the aim is shortening the length of schedules. Fault tolerance is becoming a necessary attribute in multiprocessor systems as the number of processing elements is getting larger. This paper presents a fault tolerant scheduling algorithm for task graph applications in multiprocessor systems. The algorithm is an extension of a previously proposed algorithm with a reduced communications scheme. Simulation results show the efficiency of the proposed algorithm despite its simplicity  

Networks-on-Chip (NoCs) play a crucial role in the performance of Chip Multi-Processors (CMPs). Routers are one of the main components determining the efficiency of NoCs. As various applications have different communication characteristics and hence, buffering requirements, it is difficult to make proper decisions in this regard in the design time. In this paper, we propose a traffic-aware reconfigurable router which can adapt its buffers structure to the changes in the traffic of the network. Our proposed router manages to achieve up to 18.8% and 44.4% improvements in terms of postponing saturation rate under synthetic traffic patterns, and average packet latency for PARSEC applications,... 

The continuance of Moore's law and failure of Dennard scaling force future chip multiprocessors (CMPs) to have considerable dark regions. How to use up available dark resources is an important concern for computer architects. In harmony with these changes, we must revise processor allocation schemes that severely affect the performance of a parallel on-chip system. A suitable allocation algorithm should reduce runtime and increase the power efficiency with proper thermal distribution to avoid hotspots. With this motivation, this paper proposes a power-efficient and high performance general purpose infrastructure for which a Dark Silicon Aware Processor Allocation (DSAPA) scheme is proposed... 

The utilization of the limited resources of a multiprocessor or multicomputer system is a primary performance issue crucial for the design of many scheduling algorithms. While many of the existing parallel machines benefit from a regular product network topology, almost none of the previous resource placement techniques have come to recognize and exploit this Inherent regularity. This paper introduces some novel algorithms for deriving resource placement schemes in product networks based on the assumed perfect resource placement in their underling basic graphs. © 2007 IEEE  

Models of computation abstract away a number of implementation details in favor of well-defined semantics. While this has unquestionable benefits, we argue that analysis of models solely based on operational semantics (implementation oblivious analysis) is unfit to drive implementation design space exploration. Specifically, we study the tradeoff between buffer size and streaming throughput in applications modeled as synchronous data flow (SDF) graphs. We demonstrate the inherent inaccuracy of implementation-oblivious approach, which only considers SDF operational semantic. We propose a rigorous transformation, which equips the state of the art buffer-throughput tradeoff analysis technique... 

Models of computation abstract away a number of implementation details in favor of well-defined semantics. While this has unquestionable benefits, we argue that analysis of models solely based on operational semantics (implementationoblivious analysis) is unfit to drive implementation design space exploration. Specifically, we study the tradeoff between buffer size and streaming throughput in applications modeled as synchronous data flow (SDF) graphs. We demonstrate the inherent inaccuracy of implementationoblivious approach, which only considers SDF operational semantic. We propose a rigorous transformation, which equips the state of the art buffer-throughput tradeoff analysis technique... 

Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

Mapping and Scheduling are two central and critical steps in design flow of the Networks on Chips (NoCs). They deal with implementation of the applications on NoCs. In this paper a novel energy aware algorithm, called EAMS, for mapping and scheduling of concurrent applications to NoC platforms is developed. It is considered that, the NoC architecture consists of a set of heterogeneous IP cores. The introduced algorithm finds a mapping of the tasks of the application to available IP cores so that the overall energy consumption, meeting task deadlines, is minimized  

Process variation has already emerged as a major concern in design of multi-processor system on chips (MPSoC). In recent years, there have been several attempts to bring variability awareness into the task scheduling process of embedded MPSoCs to improve performance yield. This study attempts to provide a comparative study of the current variation-aware design-time task and communication scheduling techniques that target embedded MPSoCs. To this end, the authors first use a sign-off variability modelling framework to accurately estimate the frequency distribution of MPSoC components. The task scheduling methods are then compared in terms of both the quality of the final solution and the... 

Abstract Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

Chip multiprocessors (CMPs) require a low-latency interconnect fabric network-on-chip (NoC) to minimize processor stall time on instruction and data accesses that are serviced by the last-level cache (LLC). While packet-switched mesh interconnects sacrifice performance of many-core processors due to NoC-induced delays, existing circuit-switched interconnects do not offer lower network delays as they cannot hide the time it takes to set up a circuit. To address this problem, this work introduces CIMA - a hybrid circuit-switched and packet-switched mesh-based interconnection network that affords low LLC access delays at a small area cost. CIMA uses virtual cut-through (VCT) switching for short... 

This paper proposes new architectures for data and control planes in a nanophotonic networks-on-chip (NoC) with the key advantages of scalability to large scale networks, constant node degree, and simplicity. Moreover, we propose a minimal deterministic routing algorithm for the data network which leads to small and simple photonic switches. Built upon the proposed novel topology, we present a scalable all-optical NoC, referred to as 2D-HERT, which offers passive routing of optical data streams based on their wavelengths. Utilizing wavelength routing method, Wavelength Division Multiplexing (WDM) technique, and a new all-optical control architecture, our proposed optical NoC eliminates the... 

Increasing delay and power variation has become a major challenge to designing high performance Multiprocessor System-On-Chips (MPSoC) in deep sub-micron technologies. As a result, a paradigm shift from deterministic to statistical design methodology at all levels of the design hierarchy is inevitable. In this paper, we propose a static variation-aware task scheduling and power mode selection algorithm for MPSoCs. The proposed algorithm is able to maximize the total power yield of the chip under a given performance yield constraint by searching for the optimal task scheduling and power mode selection policy for a specified multiprocessor platform. Experimental results are gathered by... 

A routing algorithm defines a route which packet traverses to get to destination. In this research we study some kind of routing algorithms that are used in internal connections networks of multi-processor and multi-computers systems. Then we discuss about some routing algorithms which have been implemented network on chip architecture. First, we present a group of routing algorithms based on various criterions, and review so-called category. Afterwards, we study adaptive and deterministic routing algorithms and express circular model applying in internal connections networks and its governing rules in order to prevent dead lock. Then we survey adaptive algorithms such as Deflection routing,... 

In this paper, we introduce a new Multi-Objective Genetic Algorithm (MOGA) for mapping a given set of intellectual property onto a Network-on-Chip architecture such that for a specific application total communication cost and energy consumption become optimized while bandwidth constraints are satisfied. As the main theoretical contribution, we first introduce a generic queuing model to estimate performance and an experimental energy consumption model during the design phase, with acceptable accuracy. Then, an efficient genetic algorithm employs these models to propose a Pareto optimal front for an application and an arbitrary topology. Experimental results show that the proposed algorithm is...