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    Process-Variation-Aware Configuration Selection of Configurable MPSOC for Power-Yield Maximization

    , M.Sc. Thesis Sharif University of Technology Izadyar, Hamideh (Author) ; Goudarzi, Maziar (Supervisor)
    Abstract
    Process Variation is seen as statistical variations in leakage current and delay of transistors in nano-scale technologies. The amount of process variations increase as the size of transistors decrease by technology scaling such that those effects can be seen in frequency of MPSoC (Multi-Processor System-on-Chip) cores and their leakage power deviation. These variations cause the tasks duration and power consumption fluctuate in different processors in an MPSoC instance. Consequently, some chip instances of the same MPSoC may consume more time and power than their considered limitations. Hence considering the process variation is necessary and required for MPSoC optimization at different... 

    Scheduling to minimize gaps and power consumption

    , Article Journal of Scheduling ; Volume 16, Issue 2 , April , 2013 , Pages 151-160 ; 10946136 (ISSN) Demaine, E. D ; Ghodsi, M ; Hajiaghayi, M ; Sayedi Roshkhar, A. S ; Zadimoghaddam, M ; Sharif University of Technology
    2013
    Abstract
    This paper considers scheduling tasks while minimizing the power consumption of one or more processors, each of which can go to sleep at a fixed cost α. There are two natural versions of this problem, both considered extensively in recent work: minimize the total power consumption (including computation time), or minimize the number of "gaps" in execution. For both versions in a multiprocessor system, we develop a polynomial-time algorithm based on sophisticated dynamic programming. In a generalization of the power-saving problem, where each task can execute in any of a specified set of time intervals, we develop a (1+23α) -approximation, and show that dependence on α is necessary. In... 

    Reduced communications fault tolerant task scheduling algorithm for multiprocessor systems

    , Article Procedia Engineering ; Volume 29 , 2012 , Pages 3820-3825 ; 18777058 (ISSN) Tabbaa, N ; Entezari Maleki, R ; Movaghar, A ; Sharif University of Technology
    Abstract
    Multiprocessor systems have been widely used for the execution of parallel applications. Task scheduling is crucial for the right operation of multiprocessor systems, where the aim is shortening the length of schedules. Fault tolerance is becoming a necessary attribute in multiprocessor systems as the number of processing elements is getting larger. This paper presents a fault tolerant scheduling algorithm for task graph applications in multiprocessor systems. The algorithm is an extension of a previously proposed algorithm with a reduced communications scheme. Simulation results show the efficiency of the proposed algorithm despite its simplicity  

    Traffic-aware buffer reconfiguration in on-chip networks

    , Article IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC, 5 October 2015 through 7 October 2015 ; Volume 2015-October , 2015 , Pages 201-206 ; 23248432 (ISSN) ; 9781467391405 (ISBN) Bashizade, R ; Sarbazi-Azad, H ; Sharif University of Technology
    IEEE Computer Society  2015
    Abstract
    Networks-on-Chip (NoCs) play a crucial role in the performance of Chip Multi-Processors (CMPs). Routers are one of the main components determining the efficiency of NoCs. As various applications have different communication characteristics and hence, buffering requirements, it is difficult to make proper decisions in this regard in the design time. In this paper, we propose a traffic-aware reconfigurable router which can adapt its buffers structure to the changes in the traffic of the network. Our proposed router manages to achieve up to 18.8% and 44.4% improvements in terms of postponing saturation rate under synthetic traffic patterns, and average packet latency for PARSEC applications,... 

    Efficient processor allocation in a reconfigurable CMP architecture for dark silicon era

    , Article Proceedings of the 34th IEEE International Conference on Computer Design, ICCD 2016, 2 October 2016 through 5 October 2016 ; 2016 , Pages 336-343 ; 9781509051427 (ISBN) Aghaaliakbari, F ; Hoveida, M ; Arjomand, M ; Jalili, M ; Sarbazi Azad, H ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2016
    Abstract
    The continuance of Moore's law and failure of Dennard scaling force future chip multiprocessors (CMPs) to have considerable dark regions. How to use up available dark resources is an important concern for computer architects. In harmony with these changes, we must revise processor allocation schemes that severely affect the performance of a parallel on-chip system. A suitable allocation algorithm should reduce runtime and increase the power efficiency with proper thermal distribution to avoid hotspots. With this motivation, this paper proposes a power-efficient and high performance general purpose infrastructure for which a Dark Silicon Aware Processor Allocation (DSAPA) scheme is proposed... 

    Distant-based resource placement in product networks

    , Article 18th International Conference on Parallel and Distributed Computing, Applications and Technologies, PDCAT 2007, Adelaide, SA, 3 December 2007 through 6 December 2007 ; January , 2007 , Pages 31-35 ; 0769530494 (ISBN); 9780769530499 (ISBN) Imani, N ; Sarbazi Azad, H ; Zomaya, A. Y ; Sharif University of Technology
    2007
    Abstract
    The utilization of the limited resources of a multiprocessor or multicomputer system is a primary performance issue crucial for the design of many scheduling algorithms. While many of the existing parallel machines benefit from a regular product network topology, almost none of the previous resource placement techniques have come to recognize and exploit this Inherent regularity. This paper introduces some novel algorithms for deriving resource placement schemes in product networks based on the assumed perfect resource placement in their underling basic graphs. © 2007 IEEE  

    Implementation-aware model analysis: The case of buffer-throughput tradeoff in streaming applications

    , Article Proceedings of the ACM SIGPLAN Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), 18 June 2015 through 19 June 2015 ; Volume 2015-June , 2015 , Pages 108-117 ; 9781450332576 (ISBN) Mirzazad Barijough, K ; Hashemi, M ; Khibin, V ; Ghiasi, S ; Sharif University of Technology
    Association for Computing Machinery  2015
    Abstract
    Models of computation abstract away a number of implementation details in favor of well-defined semantics. While this has unquestionable benefits, we argue that analysis of models solely based on operational semantics (implementation oblivious analysis) is unfit to drive implementation design space exploration. Specifically, we study the tradeoff between buffer size and streaming throughput in applications modeled as synchronous data flow (SDF) graphs. We demonstrate the inherent inaccuracy of implementation-oblivious approach, which only considers SDF operational semantic. We propose a rigorous transformation, which equips the state of the art buffer-throughput tradeoff analysis technique... 

    Implementation-aware model analysis: The case of buffer-throughput tradeoff in streaming applications

    , Article ACM SIGPLAN Notices ; Volume 50, Issue 5 , May , 2015 , Pages 103-112 ; 15232867 (ISSN) Barijough, K. M ; Hashemi, M ; Khibin, V ; Ghiasi, S ; Sharif University of Technology
    Association for Computing Machinery  2015
    Abstract
    Models of computation abstract away a number of implementation details in favor of well-defined semantics. While this has unquestionable benefits, we argue that analysis of models solely based on operational semantics (implementationoblivious analysis) is unfit to drive implementation design space exploration. Specifically, we study the tradeoff between buffer size and streaming throughput in applications modeled as synchronous data flow (SDF) graphs. We demonstrate the inherent inaccuracy of implementationoblivious approach, which only considers SDF operational semantic. We propose a rigorous transformation, which equips the state of the art buffer-throughput tradeoff analysis technique... 

    Statistical MPSoC Architecture Optimization under Process Variation

    , M.Sc. Thesis Sharif University of Technology Ghorbani, Mahboobeh (Author) ; Goudarzi, Maziar (Supervisor)
    Abstract
    In nanometer technologies, the effect of process variation is observed in Multi-Processor System on Chip (MPSoC) in terms of variation in processors‟ frequency and leakage power. Traditionally, only worst case values of the system parameters were concerned and a worst-case optimization algorithm was employed for an application under design. As previous researches have shown these algorithms are not optimal in terms of parametric yield compared with newly employed statistical optimization algorithms. In this project, we have considered the problem of simultaneously selecting MPSoC architecture (which includes type and number of processors and the communication media) and task and... 

    P2R2: Parallel Pseudo-Round-Robin arbiter for high performance NoCs

    , Article Integration, the VLSI Journal ; November , 2014 ; ISSN: 1679260 Bashizade, R ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

    P2R2: Parallel Pseudo-Round-Robin arbiter for high performance NoCs

    , Article Integration, the VLSI Journal ; Volume 50 , 2014 , pp.173–182 ; ISSN: 0167-9260 Bashizade, R ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

    An energy-aware methodology for mapping and scheduling of concurrent applications in MPSoC architectures

    , Article 2011 19th Iranian Conference on Electrical Engineering, ICEE 2011, 17 May 2011 through 19 May 2011 ; May , 2011 , Page(s): 1 ; ISSN : 21647054 ; 9789644634284 (ISBN) Rajaei, R ; Hessabi, S ; Vahdat, B. V ; Sharif University of Technology
    2011
    Abstract
    Mapping and Scheduling are two central and critical steps in design flow of the Networks on Chips (NoCs). They deal with implementation of the applications on NoCs. In this paper a novel energy aware algorithm, called EAMS, for mapping and scheduling of concurrent applications to NoC platforms is developed. It is considered that, the NoC architecture consists of a set of heterogeneous IP cores. The introduced algorithm finds a mapping of the tasks of the application to available IP cores so that the overall energy consumption, meeting task deadlines, is minimized  

    Yield-driven design-time task scheduling techniques for multi-processor system on chips under process variation: A comparative study

    , Article IET Computers and Digital Techniques ; Volume 9, Issue 4 , 2015 , Pages 221-229 ; 17518601 (ISSN) Momtazpour, M ; Assare, O ; Rahmati, N ; Boroumand, A ; Barati, S ; Goudarzi, M ; Sharif University of Technology
    Institution of Engineering and Technology  2015
    Abstract
    Process variation has already emerged as a major concern in design of multi-processor system on chips (MPSoC). In recent years, there have been several attempts to bring variability awareness into the task scheduling process of embedded MPSoCs to improve performance yield. This study attempts to provide a comparative study of the current variation-aware design-time task and communication scheduling techniques that target embedded MPSoCs. To this end, the authors first use a sign-off variability modelling framework to accurately estimate the frequency distribution of MPSoC components. The task scheduling methods are then compared in terms of both the quality of the final solution and the... 

    P2R2: Parallel pseudo-round-robin arbiter for high performance NoCs

    , Article Integration, the VLSI Journal ; Volume 50 , June , 2015 , Pages 173-182 ; 01679260 (ISSN) Bashizade, R ; Sarbazi Azad, H ; Sharif University of Technology
    Elsevier  2015
    Abstract
    Abstract Networks-on-Chip (NoCs) play an important role in the performance of Chip Multi-Processors (CMPs). Providing the desired performance under heavy traffics imposed by some applications necessitates NoC routers to have a large number of Virtual Channels (VCs). Increasing the number of VCs, however, will add to the delay of the critical path of the arbitration logic, and hence restricts the clock frequency of the router. In order to make it possible to enjoy the benefits of having many VCs and keep the clock frequency as high as that of a low-VC router, we propose Parallel Pseudo-Round-Robin (P2R2) arbiter. Our proposal is based on processing multiple groups of requests in parallel. Our... 

    An efficient hybrid-switched network-on-chip for chip multiprocessors

    , Article IEEE Transactions on Computers ; Volume 65, Issue 5 , 2016 , Pages 1656-1662 ; 00189340 (ISSN) Lotfi Kamran, P ; Modarressi, M ; Sarbazi Azad, H ; Sharif University of Technology
    IEEE Computer Society 
    Abstract
    Chip multiprocessors (CMPs) require a low-latency interconnect fabric network-on-chip (NoC) to minimize processor stall time on instruction and data accesses that are serviced by the last-level cache (LLC). While packet-switched mesh interconnects sacrifice performance of many-core processors due to NoC-induced delays, existing circuit-switched interconnects do not offer lower network delays as they cannot hide the time it takes to set up a circuit. To address this problem, this work introduces CIMA - a hybrid circuit-switched and packet-switched mesh-based interconnection network that affords low LLC access delays at a small area cost. CIMA uses virtual cut-through (VCT) switching for short... 

    Improving Performance and Power Consumption of Optical CMPs Using Inter-core Communication Prediction

    , M.Sc. Thesis Sharif University of Technology Ghane, Millad (Author) ; Sarbazi Azad, Hamid (Supervisor)
    Abstract
    Studying data flows in conventional applications of Multi-Processor System-on-Chips (MPSoCs) denotes that most of these flows are the ones that transfer huge volume of data in inter-core communications. Previous works try to present architecture for interconnection network which some paths with low power and latency are reserved (statically or dynamically). However all of the presented methods are based on subnetworks or mechanism of transferring control messages (to establish a path and tear it down after transmission of data). Optical connections with low cost, low power and high bandwidth are good candidates to reduce power consumption of Network-on-Chips (NoCs). Therefore, using optical... 

    Power efficient nanophotonic on-chip network for future large scale multiprocessor architectures

    , Article Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2011, 8 June 2011 through 9 June 2011, San Diego, CA ; 2011 , Pages 114-121 ; 9781457709944 (ISBN) Koohi, S ; Hessabi, S ; Sharif University of Technology
    2011
    Abstract
    This paper proposes new architectures for data and control planes in a nanophotonic networks-on-chip (NoC) with the key advantages of scalability to large scale networks, constant node degree, and simplicity. Moreover, we propose a minimal deterministic routing algorithm for the data network which leads to small and simple photonic switches. Built upon the proposed novel topology, we present a scalable all-optical NoC, referred to as 2D-HERT, which offers passive routing of optical data streams based on their wavelengths. Utilizing wavelength routing method, Wavelength Division Multiplexing (WDM) technique, and a new all-optical control architecture, our proposed optical NoC eliminates the... 

    Variation-aware task scheduling and power mode selection for MPSoC power optimization

    , Article Proceedings - 15th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2010, 23 September 2010 through 24 September 2010 ; September , 2010 , Pages 27-33 ; 9781424462698 (ISBN) Momtazpour, M ; Goudarzi, M ; Sanaei, E ; Sharif University of Technology
    2010
    Abstract
    Increasing delay and power variation has become a major challenge to designing high performance Multiprocessor System-On-Chips (MPSoC) in deep sub-micron technologies. As a result, a paradigm shift from deterministic to statistical design methodology at all levels of the design hierarchy is inevitable. In this paper, we propose a static variation-aware task scheduling and power mode selection algorithm for MPSoCs. The proposed algorithm is able to maximize the total power yield of the chip under a given performance yield constraint by searching for the optimal task scheduling and power mode selection policy for a specified multiprocessor platform. Experimental results are gathered by... 

    Routing algorithms study and comparing in interconnection networks

    , Article 2008 3rd International Conference on Information and Communication Technologies: From Theory to Applications, ICTTA, Damascus, 7 April 2008 through 11 April 2008 ; 2008 ; 1424417520 (e-ISBN); 9781424417513 (ISBN) Barati, H ; Movaghar, A ; Barati, A ; Azizi Mazreah, A ; Sharif University of Technology
    2008
    Abstract
    A routing algorithm defines a route which packet traverses to get to destination. In this research we study some kind of routing algorithms that are used in internal connections networks of multi-processor and multi-computers systems. Then we discuss about some routing algorithms which have been implemented network on chip architecture. First, we present a group of routing algorithms based on various criterions, and review so-called category. Afterwards, we study adaptive and deterministic routing algorithms and express circular model applying in internal connections networks and its governing rules in order to prevent dead lock. Then we survey adaptive algorithms such as Deflection routing,... 

    Multi-objective genetic optimized multiprocessor SoC design

    , Article 2008 International Symposium on System-on-Chip, SOC 2008, Tampere, 5 November 2008 through 6 November 2008 ; December , 2008 ; 9781424425419 (ISBN) Arjomand, M ; Sarbazi Azad, H ; Amiri, S. H ; Sharif University of Technology
    2008
    Abstract
    In this paper, we introduce a new Multi-Objective Genetic Algorithm (MOGA) for mapping a given set of intellectual property onto a Network-on-Chip architecture such that for a specific application total communication cost and energy consumption become optimized while bandwidth constraints are satisfied. As the main theoretical contribution, we first introduce a generic queuing model to estimate performance and an experimental energy consumption model during the design phase, with acceptable accuracy. Then, an efficient genetic algorithm employs these models to propose a Pareto optimal front for an application and an arbitrary topology. Experimental results show that the proposed algorithm is...