Sharif Digital Repository

This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is motivated by two facts: (1) Many of the produced and consumed values are narrow-width values in the embedded processors, i.e. they have leading zeros or ones in their most significant bits. This indicates that only a fraction of the circuit is performing useful operations when a particular arithmetic or logic circuit in the ALU is operating on narrow-width values; (2) other circuits of the ALU are not used, when a particular arithmetic or logic circuit is being utilized to perform a specific operation in the ALU in the... 

In this paper, a new graph product, called Edge Graph Product (EGP) is proposed by replacing each edge in the multiplicand graph by a copy of the multiplier graph via two candidate nodes. The edge product, unlike other products already proposed, results in a graph whose number of edges is numerical product of the number of the edges in the multiplicand and multiplier graphs, and the number of vertices is not equal to the numerical product of the number of vertices in the multiplicand and multiplier graphs. After formal definition of the new product, some basic properties of the product operator are studied. We then address Hamiltonian, Eulerian and routing properties of the new product, and... 

This paper introduces a low-jitter and wide tuning range delay-locked loop (DLL) -based fractional clock generator (CG) topology. The proposed fractional multiplying DLL (FMDLL) architecture overcomes some disadvantages of phase-locked loops (PLLs) such as jitter accumulation while maintaining the advantageous of a PLL as a multi-rate fractional frequency multiplier. Based on this topology, a CG with 1-2.5 GHz output frequency tuning range has been designed in a digital 0.18 um CMOS technology while the multiplication ratios are M+k/(2N C ) in which M, k, and N C are adjustable. To generate some finer ratios, k is changed periodically or randomly (by a digital delta-sigma modulator) between... 

In this paper we propose a novel structure of a discrete-time mixed-signal linear equalizer designed for analog front end of Gigabit Ethernet receivers. The circuit is an FIR filter which involves 6 taps based on a coefficient-rotating structure. Here, a simple structure is used for merging digital to analog conversion of the filter's coefficients and multipliers needed for 6 taps. This structure results in high speed and low power dissipation as well as less A/D converter complexity. Simulated in a 0.18 um CMOS technology, this equalizer operates at 125 MHz while dissipating 10 mw from a 1.8 V power supply. © 2006 IEEE  

This article introduces a novel duty-cycle control circuit (DCC) preceding a delay-locked loop (DLL)-based clock frequency multiplier preventing the output duty-cycle over process, supply voltage and temperature (PVT) variations. However, the proposed DCC eliminates the effect of input duty-cycle variation and, hence, decreases the sensitivity to the input jitter and distortion. The circuit realisation in 0.5-μm CMOS technology shows that the duty-cycle variation at the output clock is less than 2.7%, while driving the digital section of a CODEC chip and also test pads. The analysis, confirmed by measurements, shows a stable and accurate response for the proposed clock generation unit (CGU).... 

A systematic procedure of simulating charge pump based delay locked loops (DLLs) represents in this paper. The presented procedure is based on the systematic modeling of the DLL components in Matlab Simulink simulator. The system has been designed for 1Hz input clock signal that by changing the whole system scale, it can be used for every other input frequencies. The simulation results in Matlab and design considerations for DLL based frequency multiplier are presented  

This paper represents a systematic procedure of simulating charge pump based delay locked loops (DLLs). The presented procedure is based on the systematic modelling of the DLL components in Matlab simulink simulator. The system has been designed for 1Hz input clock signal that by changing the whole system scale, it can be used for every other input frequencies. The simulation results in Matlab and design considerations for DLL based frequency multiplier are presented  

In this paper, a new compact, low power and low voltage structure for CMOS analog multiplier is proposed. All of them are implemented using a compact circuit. The circuit is designed and analyzed in 0.18μm CMOS process model. Simulation results for the circuit with a 1.2V single supply show that it consumes only 25μw quiescent power with 2GHz bandwidth and 1.5% THD  

Varactor frequency multipliers often show parametric instability with increasing RF input power. Examination of the added phase noise of the varactor frequency multipliers show that, if parametric oscillations are present in the circuit, output phase noise degrades remarkably in some specific driving levels. Phase noise analysis is done by the conversion matrix method. The conversion method predicts the phase noise degradation precisely because it encounters the noise conversion by large driving levels. The added phase noise of a varactor frequency doubler with subharmonic oscillation is calculated and the simulation results are compared with measurement results. Both simulation and... 

Normal basis multiplication in finite fields is vastly utilized in different applications, including error control coding and the like due to its advantageous characteristics and the fact that squaring of elements can be obtained without hardware complexity. In this brief, we present decomposition algorithms to develop novel systolic structures for digit-level Gaussian normal basis multiplication over GF (2m). The proposed architectures are suitable for high-performance applications, which require fast computations in finite fields with high throughputs. We also present the results of our application-specific integrated circuit synthesis using a 65-nm standard-cell library to benchmark the... 

Varactor and bipolar junction transistor (BJT) frequency multipliers are a class of non-linear circuits that show parametric instability when the input drive is varied. If parametric oscillations are present in the circuit, output phase noise of the multiplier degrades remarkably in some specific driving levels. Phase noise analysis is performed by the conversion matrix method using generalised nodal analysis. The conversion method predicts the phase noise degradation precisely because it encompasses the effect of the noise sources that are modulated by the large signal drive. The added phase noise of a varactor and a BJT frequency doubler with subharmonic oscillation is calculated and the...