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n-tier-methodology
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Design of n-tier multilevel interconnect architectures by using carbon nanotube interconnects
, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 23, Issue 10 , October , 2015 , Pages 2128-2134 ; 10638210 (ISSN) ; Sarvari, R ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
In this paper, n-tier methodology is developed to design multilevel interconnect architecture of macrocells using single-wall carbon nanotube (SWCNT) bundles. Upper limit of low-bias voltage of SWCNT bundle interconnects is derived and its dependence on temperature, SWCNTs' diameter, and interconnect length is studied. Possibility of using SWCNT bundles as local interconnects at 7.5-nm technology node is discussed, and it is shown that SWCNT bundles with 1 nm diameter cannot be used at the first interconnect metal level. Using Cu and SWCNT bundles, multilevel interconnect architecture of a 7.5-nm ASIC macrocell is designed which reduces the number of metal levels by 27% and power dissipation...