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Design of a Fault Tolerant ARM-Based Processor on FPGA
, M.Sc. Thesis Sharif University of Technology ; Rashidian, Bijan (Supervisor) ; Vosughi Vahdat, Bijan (Supervisor)
Abstract
The charged particles in space strike the silicon surface of an embedded system in a satellite and cause fault occurrence in its operation. So some methods should be employed to reduce the effects of the faults. The methods that are implemented in system level are widely used because of their low cost and high reliability. The processors are responsible for performing main processes in embedded systems. On the other hand, the ARM processors are good choices for utilizing in satellites because of their low size, low power consumption and high performance. Also, FPGAs have made a major improvement in embedded system design. So with implementing ...
Operand Width Aware Hardware Reuse: A low cost fault-tolerant approach to ALU design in embedded processors
, Article Microelectronics Reliability ; Volume 51, Issue 12 , December , 2011 , Pages 2374-2387 ; 00262714 (ISSN) ; Namazi, A ; Miremadi, S. G ; Haghdoost, A ; Sharif University of Technology
2011
Abstract
This paper presents a low cost fault-tolerant technique so called OWHR (Operand Width Aware Hardware Reuse) to ALU design in embedded processors. The OWHR technique is motivated by two facts: (1) Many of the produced and consumed values are narrow-width values in the embedded processors, i.e. they have leading zeros or ones in their most significant bits. This indicates that only a fraction of the circuit is performing useful operations when a particular arithmetic or logic circuit in the ALU is operating on narrow-width values; (2) other circuits of the ALU are not used, when a particular arithmetic or logic circuit is being utilized to perform a specific operation in the ALU in the...
A multi-bit error tolerant register file for a high reliable embedded processor
, Article 2011 18th IEEE International Conference on Electronics, Circuits, and Systems, ICECS 22011, 11 December 2011 through 14 December 2011 ; December , 2011 , Pages 532-537 ; 9781457718458 (ISBN) ; Hosseini, M ; Vahdat, B. V ; Rashidian, B ; Sharif University of Technology
2011
Abstract
The vulnerability of microprocessors to soft errors is increasing due to continuous shrinking in fabrication process. Recent studies show that 1-5% of the SEUs (single event upset) can cause MBUs (multiple bit upsets). The probability of MBU generation due to SEU is increasing because of the reduction in minimum energy required to flip a memory bit in modern technologies. Register file is the most sensitive component in a microprocessor. In this paper, we present an innovative way to protect registers in a 64-bit register file for a RISC processor using extended Hamming (8, 4) code (SEC-DED code) and narrow-width values. A narrow-width value can be represented by half number of bits of the...