Sharif Digital Repository

Networks on Chip1 have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties 2 which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores on to the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs on to the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs to be... 

Networks on chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties (IP) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores onto the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs onto the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs... 

Networks on chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of intellectual properties (IP) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores onto the tiles of a chip. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs onto the tiles of the network. Different mapping algorithms have been proposed for NoCs which allocate a set of IPs to given network topologies. In these mapping algorithms, there is a restriction which limits IPs... 

Mapping and Scheduling are two central and critical steps in design flow of the Networks on Chips (NoCs). They deal with implementation of the applications on NoCs. In this paper a novel energy aware algorithm, called EAMS, for mapping and scheduling of concurrent applications to NoC platforms is developed. It is considered that, the NoC architecture consists of a set of heterogeneous IP cores. The introduced algorithm finds a mapping of the tasks of the application to available IP cores so that the overall energy consumption, meeting task deadlines, is minimized  

Coping with the intrinsic limitations of electrical networks-on-chip, optical on-chip interconnect is emerged as a promising paradigm for future high performance multi-core designs. However, optical networks-on-chip (ONoCs) are drastically vulnerable to on-chip thermal fluctuation. Specifically, electrical power consumed by processing cores induces temperature drift, which may cause false paths for optical data communication through the network. Therefore, customizing electrical power distribution throughout the chip plays a critical role for reliable data communication in ONoCs. On the other hand, chip-scale distribution of electrical power is directly affected by mapping various... 

In this paper, we present a reconfigurable architecture for networks-on-chip (NoC) on which arbitrary application-specific topologies can be implemented. When a new application starts, the proposed NoC tailors its topology to the application traffic pattern by changing the inter-router connections to some predefined configuration corresponding to the application. It addresses one of the main drawbacks of the existing application-specific NoC optimization methods, i.e., optimization of NoCs based on the traffic pattern of a single application. Supporting multiple applications is a critical feature of an NoC when several different applications are integrated into a single modern and complex...