Sharif Digital Repository

The increasing complexity of integrated circuits drives the research of new on chip interconnection architectures. Network On Chip (NoCs) are a candidate architecture to be used in future systems, due to its increased performance, reusability and scalability. A NoC is a set of interconnected switches, with IP cores connected to these switches. Different routing algorithms have been proposed for NoCs such as XY deterministic algorithm, and WF (West First), NL (North Last) and NF (Negative First) as partially adaptive algorithms. OE (Odd Even) is not based on adding virtual channels to network topologies. Unlike previous methods, which rely on prohibiting certain turns in order to achieve... 

Nowadays, a large proportion of the power consumption in high-performance multi-processor architectures on chip belongs to connections. Reducing power consumption while maintaining high efficiency in these architectures is one of the main concerns. Networks on Chip (NoC) originally were introduced to improve efficiency, but now, given the importance of power, we must provide some solutions to reduce power consumption, and delay in NOCs. Connections in chip can be divided into three categories: global, intermediate and local, while the length of global connections is almost constant in different scales, local connections are scalable. As a result improving efficiency of a small number of... 

According to power limitation on a chip and the need to simultaneously access high utilization and low power consumption, Multi-Processor System-on-Chip (MPSoC) architectures have been introduced. The major part of power consumption in a network on chip belongs to interconnects. One of the most important issues is to decrease power consumption while maintaining high utilization. The ability of optical interconnects in decreasing power consumption and increasing utilization has introduced a new architecture called optical network on chip. This architecture uses the benefits of optical signals and elements in order to transfer data. In this thesis, we introduce a new architecture with... 

Recent advances in VLSI technology have led to integrate a few billion transistors on a chip. Systems on Chip provide solutions to the design problems of these systems. As technology scales down to deep sub-micron dimensions, the delay and power consumption of global interconnects become the major bottleneck in SoC design. Networks on Chip (NoCs) have been proposed as an efficient, scalable, modular and reliable solution to provide on chip communication in large VLSI design. The market trend to mobile digital systems and battery-powered devices add power as a new dimension to VLSI design space in addition to speed and area. Interconnect wires dissipate a significant fraction of power... 

On-chip communication infrastructure in chip multiprocessors with large number of processing cores has to be scalable, consumes low power, and provides high bandwidth for hundrededs or even thousands of processing cores. In this project, to this end, the applicability of wireless network technology for on-chip communications in systems with hundreds or thousands of processing elements is investigated. We have combined wired networks (for communication between elements that are close) and wireless networks (for transmition of high volume data flows between cores that are far from each other); so different data flows achive the required bandwidth and point to point delay is reduced. Also, a... 

According to Moor’s law, the number of transistors per chip would double every 1.5 years. It means that the number of processors, memory and hardware cores available on the chip also increases. In SoC, a number of IP cores and communication links or buses are integrated on a chip. According to inefficiency of the interconnection bus used in SoCs for a large number of processors, NoC has been introduced in the beginning of the current decade. In the NoC paradigm a router-based network is used for packet switched on-chip communication among cores. A typical NoC architecture will provide a scalable communication infrastructure for interconnecting cores. One of the most important features of... 

Three dimensional or vertical integration is a new way of increasing the performance and expanding the capabilities of modern integrated circuits. Using this technology, 3D Networks on Chip has been proposed as one of the novel research fields and has been receiving a lot of attention. Using the third dimension, different topologies could be implemented in these chips and positive effects of this integration like decreasing the length of interconnections and decreasing the communication latency as the result of that could be utilized. In addition to common topologies like mesh and torus, it is possible to implement other structures in three dimensional integration. Topologies with lower... 

Emerging memory technologies such as STT-RAM, PCM and resistive RAM are probable technologies for caches and main memories of the future multi-core architectures. This is because of their high density, low leakage current and non-volatility. Nevertheless, the overhead of latency and energy consumption of write operation in these technologies are the main open problems. Previous works have suggested various solutions, in architecture and circuit levels, to reduce the writing overheads. In this research, we study the integration of STT-RAM in 3-dimensional multi-core environments; and propose solutions to address the problem of writing overheads when using this technology in cache... 

ITRS shows next generation of Multiprocessor System on Chip (MPSoCs) designs will contain hundreds of heterogeneous cores, running at different speeds and voltage levels. Networks-On-Chip (NoC) provide a structured way of realizing interconnections on silicon, and obviate the limitations of bus-based solution. As the number of components in MPSoCs increases, the interconnect schemes based on NoC approach are increasingly used. However, NoC designs have many power, area, and performance trade-offs in topology, buffer sizes, routing algorithms and flow control mechanisms, hence the study of new NoC designs can be very time-intensive.
To address these challenges, we propose a new... 

Growing transistor counts, limited power budgets, and the breakdown of voltage scaling are currently conspiring to create a utilization wall that limits the fraction of a chip that can run at full speed at one time. This concept is the basis of the Dark Silicon definition. To address this issue, it is needed a structure to guaranty Limited power budget and obtain sufficient flexibility and performance for different applications with variety communication needs. Regarding to this structure, our aim is to present a platform for Networks-on-Chip that uses clustering and resource sharing among cores. Moreover, as task mapping on processing elements in NOCs is one of the most effective way to... 

The exponential increase in power density within a chip due to higher frequency of operation in recent years (Moor's law) is a major limiting factor for designers. Increasing the number of parallel cores instead of increasing the frequency of operation is a possible solution. The design of connections within the cores can be followed by the old process but the global interconnectsbetween the cores instead of point to point can be replaced byNetwork-on-Chip (NoC). In this thesis, The dimensions of global interconnects in many-core chips are optimized for maximum bandwidth density and minimum delay taking into account network-on-chip router latency and size effects of coppe. The optimal... 

Combination of 3D IC technology and network on chip (NoC) is an effective solution to increase system scalability, and also alleviate the interconnect problem in large scale integrated circuits. However, due to the increased power density in 3D NoC systems and the destructive impact of high temperatures on chip reliability, applying thermal management solutions becomes crucial in such circuits. Since hardware thermal control techniques, such as DVFS, can cause significant degradation on chip performance, in this thesis we propose a runtime distributed migration algorithm based on game theory to balance the heat dissipation among processing elements (PEs) in 3D NoCs. The objective of this... 

Network-on-Chip has been introduced as an effective and scalable communication infrastructure for multiprocessor systems. Nowadays, different applications with various traffic patterns and timing demands must be executed on these platforms. However, static NoCs only perform well for specific domain of applications. Therefore, for different applications, parameters of the system should be designed for the worst case scenario that is considered to be executed on it, or for each domain of application, a chip should be fabricated. The first solution leads to underutilization of system resources and the second one imposes cost of refabricating. Consequently, designers have offered different... 

Networks on Chip have been proposed as a solution to mitigate complex on-chip communication problems. NoCs are composed of IP cores (or processing elements) which are interconnected by on-chip switching fabrics. A step in the design process of NoCs is hardware virtualization which is mapping the IP cores on to the tiles of chips. The communication among the IP cores greatly affects the performance and power consumption of NoCs which itself is deeply related to the placement of IPs on to the tiles of the network. Different mapping algorithms have been proposed for Network on Chips which allocate a set of Intellectual Properties (IPs) to determined network topologies. In these mapping... 

Due to the rapid growth of technology, the number of cores on a single chip has increased, caused thousands (or millions) of transistors being tight in a new layout consequently. Technology scaling arise the sensitivity and likelihood of faults. Thus, fault management is one of the important challenging issues in multiple core design we should face. Faults can be permanent, transient, and intermittent. Apart from the fact that how and when a fault occurs, supporting a fault-tolerant or fault-prevention routing is a must in NoCs. To target mentioned problem, we have proposed two routing algorithm in this thesis. The first algorithm is FaulToleReR, which is a reconfigurable fault (faults can... 

Network-on-Chip (NoC) is a promising on-chip communication paradigm which targets the scalability and predictability problems of the traditional on-chip mechanisms. However, it has been shown that, in future technologies (especially 22 nm technology), the power consumption of the current NoCs is about 10 times higher than the power budget can be devoted to them. Application-specific optimization is one of the most effective approaches to bridge the exiting gap between the current and the ideal NoC power consumptions. However, almost all existing application-specific customization methods try to customize NoCs for... 

Three dimensional or vertical integration is a new way of increasing the performance and expanding the capacities of modern integrated circuits. Using this technology, 3D Networks on Chip has been proposed as one of the novel research fields and has been receiving a lot of attention. 3D Networks on chip have a lot of benefits such as capability of large scale integration, increasing the density of elements on chip and expanding the dimensions of chips. Large scale integration and increasing density of elements will cause more consumption of energy. This more energy consumption will cause high temperature in chips. Although high temperature has been managed in 2D networks, but necessity of... 

Combination of 3D stacking and network-on-chip (NoC), known as 3D NoC, has some advantages such as reduced propagation delay, chip area and interconnect, and power consumption, and bandwidth increase. Despite these advantages, the increased power density per chip area due to area decrease causes thermal problems in 3D NoCs to be more critical than 2D NoCs. Therefore, design of temperature management algorithms is essential for these systems. One of the dynamic thermal management techniques is task migration that balances generated thermal among cores.In this thesis, we propose a task migration scheme using feedback control for 3D NoCs. The main purpose of this scheme is to decrease the peak...