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noise-shaping
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Non-destructive testing of cracks using eddy currents and a generalized regression neural network (GRNN)
, Article 2003 IEEE International Antennas and Propagation Symposium and USNC/CNC/URSI North American Radio Science Meeting, Columbus, OH, 22 June 2003 through 27 June 2003 ; Volume 2 , 2003 , Pages 239-242 ; 02724693 (ISSN) ; Barkeshi, K ; Sharif University of Technology
2003
Abstract
A method to effectively estimate crack shapes in conductive surfaces is proposed. Its performance is also robust in the presence of noise. Comparison of the results from the GRNN with those obtained from the feed-forward network indicates that the GRNN is trained and identifies the size and the shape of the cracks faster than the feed-forward network
A new low-power sigma-delta modulator with the reduced number of op-amps for speech band applications
, Article Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, Bangkok, 25 May 2003 through 28 May 2003 ; Volume 1 , 2003 , Pages I1033-I1036 ; 02714310 (ISSN) ; Sahandi, F ; Mojtaba Atarodi, S ; Sharif University of Technology
2003
Abstract
An area and power-efficient second order sigma-delta modulator is presented. At system level, we propose a new single-loop single-stage modulator that uses only one class-AB op-amp to realize a second order noise shaping for speech band applications. The modulator shows 86 dB DR in 4 kHz speech bandwidth. It consumes 125 μw from a 2.5 V supply
A new single-loop single-stage low power sigma-delta modulator
, Article 14th International Conference on Microelectronics, ICM 2002, 11 December 2002 through 13 December 2002 ; Volume 2002-January , 2002 , Pages 215-218 ; 0780375734 (ISBN) ; Sahandi, F ; Mojtaba Atarodi, S ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2002
Abstract
This paper presents a new single-loop single-stage second order sigma-delta modulator. The circuit based on switched capacitor components just uses one Op-Amp to realize second order noise shaping. The modulator demonstrated 85 dB DR in 8kHz bandwidth, dissipating 135 μW from a 2.5 V supply. © 2002 IEEE
A reduced complexity 3 rd order digital delta-sigma modulator for fractional-N frequency synthesis
, Article Proceedings - 17th International Conference on VLSI Design, Concurrently with the 3rd International Conference on Embedded Systems Design, Mumbai, 5 January 2004 through 9 January 2004 ; Volume 17 , 2004 , Pages 615-618 ; 10639667 (ISSN) ; Atarodi, S. M ; Bornoosh, B ; Kusha, A. A ; Sharif University of Technology
2004
Abstract
A reduced complexity third-order digital delta-sigma modulator is presented. The modulator consists of two cascaded sections to produce proper shaping of quantization noise with minimum hardware. A new architecture for a digital third-order delta-sigma modulator based on Ritchie structure is proposed. The measurement results show 94dB SNR and 65% dynamic range
Design and Implenentation of a Bandpass Delta-sigma Modulator Using High-Q N-path Filter
, M.Sc. Thesis Sharif University of Technology ; Atarodi,Mojtaba (Supervisor) ; Sharifkhani, Mohammad (Co-Supervisor)
Abstract
Delta-Sigma Analog-to-Digital converters have been positioned themselves as robust reliable converters so far. The magic Of extracting high resolutions from low bit ADC has made them popular between designers. Previously, the noise-shaping magic was used in high-resolution applications such as high-quality audio signal converters. However, as the technology scales and proceeds, these converters are approaching RF applications, too. Power and OSR trade-off limits this progress. To increase OSR in bandpass delta-sigma modulators, more power should be consumed to increase the quality factor of loop filters. In this thesis, a systematic approach has been utilized. An n-path filter is employed...
Improved unity-STF sturdy MASH ΣΔ modulator for low-power wideband applications
, Article Electronics Letters ; Volume 51, Issue 23 , November , 2015 , Pages 1941-1942 ; 00135194 (ISSN) ; Sadughi, S ; Sharif University of Technology
Institution of Engineering and Technology
2015
Abstract
A novel sturdy multi-stage noise-shaping sigma-delta modulator that cancels the first-stage quantisation error at the output of the modulator is presented. Since any stage of the modulator has unity signal transfer function, the modulator would be very robust to circuit non-idealities such as finite op-amp gain. Furthermore, the signal processing timing issue in the critical paths of the proposed topology has been relaxed due to shifting the delay of the last integrator to the feedback path of the modulator. Moreover, this topology can be implemented in the circuit level by a fewer active blocks. Therefore, it practically would be suitable for low-voltage and low-oversampling applications....
A novel architecture of pseudorandom dithered MASH digital delta-sigma modulator with lower spur
, Article Journal of Circuits, Systems and Computers ; Volume 25, Issue 7 , 2016 ; 02181266 (ISSN) ; Frashidi, E ; Sadughi, S ; Sharif University of Technology
World Scientific Publishing Co. Pte Ltd
Abstract
A Digital Delta Sigma Modulator (DDSM) is a Finite State Machine (FSM); it is implemented using finite precision arithmetic units and the number of available states is finite. The DDSM always produces a periodic output signal when the input is constant. This paper proposes a novel method of applying periodic dither to a DDSM in order to obtain minimized spurious tones. The effects of adding the pseudorandom dither signal in different stages within the proposed Multi-Stage noise Shaping (MASH) modulator are expressed in the equations, and the results are compared. We present results regarding the periodicity of the quantization noise produced by a MASH modulator with a constant input and a...
A noise shaped flash time to digital converter for all digital frequency synthesizers
, Article ECCTD 2009 - European Conference on Circuit Theory and Design Conference Program, 23 August 2009 through 27 August 2009 ; 2009 , Pages 898-901 ; 9781424438969 (ISBN) ; Atarodi, M ; Sharif University of Technology
Abstract
Reduction of Time to Digital Converter (TDC) quantization related phase noise is one of the most important challenges in all digital frequency synthesizer design. In this paper, a new structure is proposed to shape the quantization noise of flash TDCs. To verify effectiveness of the proposed general noise shaping technique, it is employed on a single delay chain flash TDC. To compensate the process variation effects on the implemented circuits, a calibration technique is also proposed. The design is implemented in 0.18μm CMOS technology. Simulations show effective noise shaping of output quantization noise
Analysis of C-2C DAC Mismatch Effects in SAR ADCs
, M.Sc. Thesis Sharif University of Technology ; Sharif Khani, Mohammad (Supervisor)
Abstract
Analog to digital converters is one of the main building blocks of today's circuits. These circuits play an important role in signal processing. Since these circuits consist of analog and digital sections, a large percentage of the power consumed in a circuit is allocated to this section. Therefore, in applications such as medical devices, wearable applications and wireless technology where power control is very important and necessary, reducing the power of analog to digital converters is very important. One of the simplest analog-to-digital converters from the design point of view is Successive Approximation Register (SAR) analog-to-digital converters. This type of analog-to-digital...