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A high speed, high resolution, low voltage currentmode sample and hold
, Article IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005, Kobe, 23 May 2005 through 26 May 2005 ; 2005 , Pages 1417-1420 ; 02714310 (ISSN) ; Bakhtiar, M. S ; Sharif University of Technology
2005
Abstract
A low voltage current mode sample and hold (S/H) in 0.18μm technology with 1.5v supply voltage is presented. This S/H has 12-bit linearity, i.e., gain and nonlinearity errors of S/H are less than 0.02μA for 100uA input current. Maximum sampling rate for this structure is 100 MHz (using double sampling technique). © 2005 IEEE
Analysis of integral non-linearity errors in two-step analogue-to-digital converters
, Article IET Circuits, Devices and Systems ; Volume 6, Issue 1 , January , 2012 , Pages 1-8 ; 1751858X (ISSN) ; Medi, A ; Sharif University of Technology
Abstract
A new method for modelling and analysis of non-linearity errors caused by the capacitor mismatches and op-amp non-idealities in two-step analogue-to-digital converters (ADCs) is presented. Analytical formulas for estimation of the ADC integral non-linearity (INL) are derived. Using the proposed method, the ADC INL can be calculated in terms of the capacitor mismatches standard deviations. Therefore time-consuming Monte Carlo simulations which are conventionally used to evaluate the effect of random capacitor mismatches on the ADC linearity can be avoided. The effect of op-amp non-idealities, which are frequently examined by the circuit-level simulations, can also be evaluated using the...