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An Intelligent L2 Management Method in GPUs
, M.Sc. Thesis Sharif University of Technology ; Sarbazi Azad, Hamid (Supervisor)
Abstract
To capture on-chip memory locality, tolerate off-chip memory latency, and expeditiously process memory-bound GPGPU applications, Graphics Processing Units (GPUs) introduce a local L1D cache and a shared L2 cache within and between streaming multiprocessors (SMs), respectively. The L2 cache solves the problem of data coherency and sharing between SMs (unlike the L1D cache). Prior work shows that loading all data into the L2 cache without a proper mechanism to manage the input data rate, poses some challenges (e.g., cache contention/trashing, increased write-back traffic, and bandwidth inefficiency) and ultimately puts a lot of pressure on off-chip memory. In this paper, we make the...
Assertion-based debug infrastructure for SoC designs
, Article 19th International Conference on Microelectronics, ICM, Cairo, 29 December 2007 through 31 December 2007 ; 2007 , Pages 137-140 ; 9781424418473 (ISBN) ; Babagoli, M ; Hessabi, S ; Sharif University of Technology
2007
Abstract
In this paper, an infrastructure for debug of complex SoCs that employs assertions is introduced. The proposed infrastructure combines traditional off-chip analysis techniques with on-chip at-speed debug facilities. The main part of on-chip debug hardware consists of data and transaction monitors. The monitor hardware is automatically generated by synthesizing the assertions that were used for verification and validation before manufacturing. We have integrated the proposed method in a system-level design methodology. By synthesizing various assertions from different kinds in a case study we have studied the overhead of our method. © 2007 IEEE
Effect of varying aspect ratio on relative stability for graphene nanoribbon interconnects
, Article Applied Mechanics and Materials, 24 July 2012 through 26 July 2012 ; Volume 229-231 , November , 2012 , Pages 205-209 ; 16609336 (ISSN) ; 9783037855102 (ISBN) ; Faez, R ; Nasiri, S. H ; Davoodi, B ; Sharif University of Technology
2012
Abstract
Achieving dense off-chip interconnection with satisfactory electrical performance is emerging as a major challenge in advanced system engineering. Graphene nanoribbons (GNRs) have been recently proposed as one of the potential candidate materials for both transistors and interconnect. In addition, development is still underway for alternative materials and processes for high aspect ratio (AR) contacts. Studding the effect of varying aspect ratio on relative stability of graphene nanoribbon interconnects is an important viewpoint in performance evaluation of system. In this paper, Nyquist stability analysis based on transmission line modeling (TLM) for GNR interconnects is investigated. In...