Sharif Digital Repository

In this paper, we propose a new voltage controlled oscillator (VCO) with a high oscillation frequency yet low power consumption. The oscillator which is a single stage circuit has a low phase noise due to reduced noise sources. To evaluate the performance parameters, the oscillator was simulated in a 0.18-μm standard CMOS process. The results show that the oscillation frequency of VCO may vary between 4.66-5.9 GHz. Also, the phase noise of the VCO at oscillation frequency of 5.6 GHz is -99.7 dBc at 1 MHz offset frequency. Also, the power consumption was 4.8 mW at the same oscillation frequency. © 2007 IEEE  

For the last few decades, phase-noise (PN) improvement of VCOs has been an intriguing problem and remains as one of the challenges in transceiver design. PN in CMOS VCOs, especially close-in PN, greatly suffers from flicker noise. The flicker noise can even degrade the PN at higher offset frequencies (∼1MHz). The close-in PN is important in many communication applications. For instance, IEEE 802.11a/b/g requires a very low PN at 10kHz offset frequency [1] and the PN performance at 100kHz is critical in cellular and Wi-Fi MIMO applications. In addition to the PN performance, oscillators with lower power consumption and smaller area are always on demand  

In this paper, the impact of both time offsets (TOs) and carrier frequency offsets (CFOs) on the average output signal-to-interference-plus-noise ratio (SINR) in a frequency selective channel is investigated with a novel approach. First, TOs are partitioned into five cases based on how they occur. Then the mathematical models for different cases are derived. Considering CFOs and benefiting from the obtained models, closed-form expression for the SINR in each case is derived. It is proved that, SINR is independent of the observed subcarrier for the given TO and CFO. Besides, it is shown that the performance of the affected system deteriorates rapidly as the number of subcarriers increases. It... 

This paper deals with timing and frequency synchronization in orthogonal frequency-division multiplexing (OFDM) systems. A robust multistage scheme that works in the time domain, independent of the preamble structure, is proposed. After coarse-timing estimation, joint timing and integer frequency synchronization is performed. Then, fractional frequency correction is carried out, and finally, fine-timing estimation completes the synchronization process. The new timing estimation method is flexible and can be adjusted according to the degree of channel distortion. Furthermore, frequency synchronization is efficiently accomplished with an estimation range that is as large as the bandwidth of... 

New results regarding phase and amplitude noise analysis in microwave oscillators for moderate offset frequencies from the carrier are presented. Although the phase noise process in an oscillator is a large signal non-stationary process, it is proved that for the purpose of phase noise calculations for moderate offset frequencies, the phase noise process can be considered as a small signal stationary process and by this assumption, a valid approximation of the phase noise spectrum at these offset frequencies is obtained. By this consideration, a simplified approach for the purpose of the phase and amplitude noise spectrum calculations, at far enough from the carrier offset frequencies, by... 

A low-power fully linear integrated CMOS LC-based Digitally Controlled Oscillator is presented. The DCO operates in 5.2 GHz to 5.8 GHz range for using in IEEE 802.11a wireless applications. The system has been designed using 65 nm CMOS technology and 1.2 V supply voltage. By applying a proposed filter in DCO architecture −133.41 dBc/Hz phase noise at 1 MHz offset frequency from the fundamental carrier is achieved. The code generator and digital to analog converter designed to provide the high precision voltage required for fine-tuning. The output frequency swept through 10 control bits with 100 KHz resolution. The measured RMS jitter (∑ [1 KHz – 2 GHz]) from 5.8 GHz carrier is 1.65 fs. The... 

In this paper, a low power receiver for medical implant communication service (MICS) is presented. Low power design is vital in the MICS applications since the implanted chip has to work for a long time without the need to change its battery. As a result, a merged N-path low noise amplifier (LNA) and mixer block is proposed. In this structure, the LNA and down-conversion mixer share a transconductance to lower the overall power consumption. An N-path feedback is utilized around the shared transconductance not only to improve the LNA selectivity and relax the linearity requirements but also to downconvert the radio frequency (RF) component and create the intermediate frequency (IF) signal. In...