Sharif Digital Repository

In this paper, we propose the first comprehensive mathematical performance model for product networks where fully adaptive routing is applied. Besides the generality of this model which makes it suitable to be used for any product graph, our analysis shows that the proposed model exhibits high accuracy. Simulation results show the validity and accuracy of the model even in heavy traffic and saturation region, where other models have severe problems for prediction. © 2007 IEEE  

Grid computing is a type of parallel and distributed system that provides the possibility of sharing, choosing and collecting the autonomous resources (such as computer, software, databases, and equipments) that are distributed geographically. Resource discovery is one of the key subjects in distributed systems and especially Grids. We should consider that Grid consists of different applications that each of them consist of different hardware and software resources, therefore recognizing these resources is important in a Grid system. Classical approaches to Grid resource discovery are either centralized or hierarchical [1] (and will maybe prove inefficient as the scale of Grid systems... 

The widespread application of deep sub-micron and multilayer routing techniques makes the interconnection parasitic influence become the main factor to limit the performance of VLSI circuits. Therefore, fast and accurate 3D capacitance extraction is essential for ultra deep sub-micron design (UDSM) of integrated circuits. Parallel processing provides an approach to reducing the simulation turn-around time. In this paper, we present parallel formulations for 3D capacitance extraction based on P-FFT algorithm, on a personal computer (PC) or on a network of PCs. We implement both vector and parallel versions of 3D capacitance extraction algorithm simultaneously and evaluate our implementation... 

Load Balancing has many applications in various systems, but specifically plays a major role in the efficiency of parallel and distributed systems. In these systems, by load balancing we mean scheduling the jobs in a way that every job could be executed concurrently while it is mapped to a processing unit, such as a processor (in a multi-processor system) or a computer (in a grid computer). By developing effective methods the whole program time execution will be decreased and process utilization will be optimized. In this paper, a solution is proposed for dynamic load balancing. Because of the NP-hard nature of the problem, heuristic methods are desired. A simple scheduling method, Round... 

Given an undirected graph with weights associated with its edges, the Steiner tree problem consists of finding a minimum weight subtree spanning a given subset of (terminal) nodes of the original graph. Minimum Spanning Tree Heuristic (MSTH) is a heuristic for solving the Steiner problem in graphs. In this paper we first review existing algorithms for solving the Steiner problem in graphs. We then introduce a new parallel version of MSTH on three dimensional mesh of trees architecture. We describe our algorithm and analyze its time complexity. The time complexity analysis shows that the algorithm's running time is O(lg2 n) which is comparable with other existing parallel solutions. © 2007... 

Topology control protocols construct a logical topology out of the physical communication graph. Logical topology is maintained by logical neighbor lists in every node. Logical topology is used by several upper-layer protocols as a substantial communication map and is prone to link breakages due to node mobility which compels the periodic re-execution of the topology control protocol in so called "Hello" intervals. The problem addressed in this paper is determining the maximum "Hello" interval preserving the connectivity with high probability which is not extensively concerned yet. The simplest form of topology control, homogeneous topology control, is chosen for start. Two connectivity... 

According to International Technology Roadmap for Semiconductors (ITRS), before the end of this decade, we will be entering the era of a billion transistors on a single chip. The major threat toward the achievement of billion transistor on a chip is poor scalability of current interconnect infrastructure. With the advent of "Network on Chip (NoC)" various characters and methodologies of traditional networks were hardly considered on-chip. Failure, Power and Area are the major concepts that should be considered when migrating from traditional interconnection networks to NoCs. In this paper we study the effects of faulty links and nodes on power and performance of mesh based NoC, Also several...