Sharif Digital Repository

In this thesis, A novel approach for ¼-rate clock Phase Detector (PD) structure for Phase Locked Loop (PLL)-based Clock and Data Recovery (CDR) is proposed. In this approach, the retimed data is generated within the circuit and no extra circuit is needed. Another advantage of this topology is that the error and reference signals are independent of delay time through gates and no extra replica circuit is needed to compensate the delay. This topology results in a lower power circuit and smaller area for high speed application compared to conventional topologies  

Low noise oscillator design has always been an important subject. Oscillators aren’t usually applicable in free-run mode. Thermal instability and high phase noise level near the carrier frequency are some of the reasons which makes the oscillator not to be used in free-run mode. Using the oscillator in a phase locked loop overcomes the mentioned problems. The oscillator considered in this project, uses a SAW resonator(1GHz). Low phase noise level at far carrier offsets, is the main feature of this oscillator. However, the near carrier phase noise isn’t good enough. Consequently, using a phase locked loop, we lock the oscillator to a low noise and stable source in order to increasing thermal... 

In this thesis first of all we investigate phase noise and it's generation factors. Then we design and implement an ultra low phase noise oscillator. To do this, an ultra low phase noise oscillator which is tunable in 1-2GHz with 100MHz steps will be designed. The outline of the circuit is as follows: at the first we design a VCO which is ultra low phase noise and mechanically tunable in 1-2GHz by means of rotation of a handle. Then a phase locked loop will be built with the help of an ultra low phase noise OCXO at 100MHz and one SPD1 which generates harmonics of OCXO's output frequency. For the next, design and implementation of a 1.6GHz oscillator with fixed output frequency has been done.... 

Growing demand for increased data transmission in communication systems and the internet, has intensified the need to increase the bandwidth of high speed transceivers. One of the main elements in high speed receivers is the clock and data recovery circuit which guarantees the transfer of data with high reliability. In this thesis, the design of a clock and data recovery circuit for high frequency applications is considered. The aim of this project is the design of a circuit with low power and low jitter for high-speed input data. A new four stage LC ring oscillator is designed that works at the quarter rate of the input. A new idea for the design of the binary phase detectors has also been... 

Some applications need fast locking clock and data recovery circuits for example the circuits that operate in burst mode must lock to the data packets which are transmitting from different transmitters very quickly and in just a few bit times. In such applications open-loop clock and data recovery circuits are used because lock time in closed-loop clock and data recovery circuits is usually much longer.
In this thesis a new open loop clock and data recovery circuit based on injection locking method has been proposed. This circuit can be used in applications such as passive optical networks that need fast locking. In this architecture a super harmonic injection-locked frequency divider...