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    A novel three-phase magnitude-phase-locked loop system

    , Article IEEE Transactions on Circuits and Systems I: Regular Papers ; Volume 53, Issue 8 , 2006 , Pages 1792-1802 ; 10577122 (ISSN) Karimi Ghartemani, M ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2006
    Abstract
    A novel three-phase magnitude-phase-locked-loop system (3MPLL) for use in the general area of three-phase (power, energy and power electronic) systems is introduced. The proposed 3MPLL suppresses the noise and distortion from the input signal, mitigates the unbalance, and synthesizes the instantaneous positive-sequence component of the input signal; thus it operates as a nonlinear adaptive notch (or band-pass) filter. The 3MPLL also adaptively tracks and estimates the magnitude, phase angle, and frequency of the input signal; thus, its operation as a nonlinear state estimator. Characteristics of the 3MPLL including its mathematical equations as well as steady-state and dynamic responses are... 

    Performance limits of optical clock recovery systems based on two-photon absorption receiver structure [electronic resource]

    , Article IEEE Journal of Selected Topics in Quantum Electronics ; Vol.14, No.3, PP. 963-971 May/June 2008 Zarkoob, H ; Salehi, J. A ; Sharif University Of Technology
    Abstract
    In this paper, we analyze and discuss the performance limits of optical clock recovery systems using a phase-locked loop (PLL) structure with nonlinear two-photon absorption (TPA) phase detection scheme. The motivation in analyzing the aforementioned optical PLL with TPA receiver structure is due to a recent successful experiment reported in . We characterize the mathematical structure of PLLs with TPA, so as to evaluate the performance limits on optical clock recovery mechanism. More specifically, we identify two intrinsic sources of phase noise in the system namely, the on- off nature of the incoming data pulses and the detector's shot noise that ultimately limit the performance of the... 

    Statistical definition of locking bandwidth in an array of synchronised microwave oscillators

    , Article IET Microwaves, Antennas and Propagation ; Volume 2, Issue 1 , 2008 , Pages 74-81 ; 17518725 (ISSN) Hajian, H ; Banai, A ; Farzaneh, F ; Sharif University of Technology
    2008
    Abstract
    Arrays of N weakly coupled oscillators are considered in different configurations. The locking bandwidth for these arrays is defined statistically. Various factors affecting the locking bandwidth and the effect of the coupling network topology on locking bandwidth are studied by solving the dynamic equations of the array numerically. The analytical locking bandwidth for two configurations of arrays is computed and the results are compared with the numerical solution of dynamic equations. © The Institution of Engineering and Technology 2008  

    Theoretical considerations in designing ultra-high speed all-optical clock recovery using fiber optical parametric amplifiers

    , Article Journal of Lightwave Technology ; Vol. 32, issue. 15 , August , 2014 , pp. 2678-2689 ; ISSN: 07338724 Damani, R ; Salehi, J. A ; Sharif University of Technology
    Abstract
    In this paper, a new all-optical phase-locked loop (OPLL) in a TDM system is proposed and analyzed. The scheme relies on using fiber optical parametric amplifier (FOPA) device models and theories. In the proposed OPLL, the local clock pulse stream and the received data signal pulses are fed into the FOPA as its pump and amplified signals, respectively. The power of the resulting, relatively, strong idler signal depends on the phase difference between the local clock and the received data signal pulses, and it is used to reveal the OPLL's error signal. We characterize the mathematical structure of the proposed OPLL and identify its three intrinsic sources of phase noises namely, randomness of... 

    Synchronization-Phase Alignment of All-Digital Phase-Locked Loop Chips for a 60-GHz MIMO Transmitter and Evaluation of Phase Noise Effects

    , Article IEEE Transactions on Microwave Theory and Techniques ; Volume 67, Issue 7 , 2019 , Pages 3187-3199 ; 00189480 (ISSN) Salarpour, M ; Farzaneh, F ; Staszewski, R. B ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2019
    Abstract
    A phase-coherent technique for multiple all-digital phase-locked loops (ADPLLs) is presented and developed in this paper to target a 57-63-GHz multiple-input multiple-output (MIMO) transmitter (TX) with a digital beam-steering capability. The ADPLL TX chains are first fabricated in nanoscale CMOS and then time-synchronized and frequency-phase locked by a field-programmable gate array (FPGA) evaluation board. The calibration approach for phase alignment is carried out using a cancellation method to acquire the out-of-phase state within two ADPLLs. The accuracy of beam steering and phase alignment is investigated and analyzed based on a time-domain model for ADPLL to consider the impact of... 

    , M.Sc. Thesis Sharif University of Technology Miraki, Mohammad (Author) ; Sharif Khani, Mohammad (Supervisor)
    Abstract
    With the advancement of the technology, Design of low power devices such as biomedical systems, wireless sensor network, portable devices and … has received more attention. Digitally controlled oscillator (DCO) is one of the sub-blocks in systems such as all digital phase locked loop (ADPLL) which consumes the major power of the system. Therefore, Design of a low power DCO will decrease the power consumption of the system significantly.
    In this thesis, a digital control oscillator which is ultra low power is design for system on chip applications. Coarse-Fine architecture is used with binary weighted cells in this design. For the Coarse tuning stage, a new delay cell is proposed which... 

    Clock and Data Recovery Circuit For High Speed Serial Communication

    , M.Sc. Thesis Sharif University of Technology Mousavi, Hassan (Author) ; Hajsadeghi, Khosroo (Supervisor)
    Abstract
    In this thesis, A novel approach for ¼-rate clock Phase Detector (PD) structure for Phase Locked Loop (PLL)-based Clock and Data Recovery (CDR) is proposed. In this approach, the retimed data is generated within the circuit and no extra circuit is needed. Another advantage of this topology is that the error and reference signals are independent of delay time through gates and no extra replica circuit is needed to compensate the delay. This topology results in a lower power circuit and smaller area for high speed application compared to conventional topologies  

    Design and Fabrication of Phase Locked Loop Circuit Using SAW Oscillator

    , M.Sc. Thesis Sharif University of Technology Olad Dilmaghanian, Majid (Author) ; Banai, Ali (Supervisor)
    Abstract
    Low noise oscillator design has always been an important subject. Oscillators aren’t usually applicable in free-run mode. Thermal instability and high phase noise level near the carrier frequency are some of the reasons which makes the oscillator not to be used in free-run mode. Using the oscillator in a phase locked loop overcomes the mentioned problems. The oscillator considered in this project, uses a SAW resonator(1GHz). Low phase noise level at far carrier offsets, is the main feature of this oscillator. However, the near carrier phase noise isn’t good enough. Consequently, using a phase locked loop, we lock the oscillator to a low noise and stable source in order to increasing thermal... 

    Design and Implementation of a 1-2 GHz Ultra Low Phase Noise Phase Locked Loop using SPD

    , M.Sc. Thesis Sharif University of Technology Abedanzadeh, Amir Hossein (Author) ; Banaei, Ali (Supervisor)
    Abstract
    In this thesis first of all we investigate phase noise and it's generation factors. Then we design and implement an ultra low phase noise oscillator. To do this, an ultra low phase noise oscillator which is tunable in 1-2GHz with 100MHz steps will be designed. The outline of the circuit is as follows: at the first we design a VCO which is ultra low phase noise and mechanically tunable in 1-2GHz by means of rotation of a handle. Then a phase locked loop will be built with the help of an ultra low phase noise OCXO at 100MHz and one SPD1 which generates harmonics of OCXO's output frequency. For the next, design and implementation of a 1.6GHz oscillator with fixed output frequency has been done.... 

    Modeling, control and islanding detection of microgrids with passive loads

    , Article Proceedings of EPE-PEMC 2010 - 14th International Power Electronics and Motion Control Conference, 6 September 2010 through 8 September 2010 ; September , 2010 , Pages T11107-T11112 ; 9781424478545 (ISBN) Popov, M ; Karimi, H ; Nikkhajoei, H ; Terzija, V ; Sharif University of Technology
    2010
    Abstract
    This paper presents a control scheme for microgrids with passive loads. The existing control techniques for distributed generation systems are designed to operate either in the grid-connected or in the islanded mode. In the grid-connected mode of operation, a currentcontrolled scheme based on d-q variables is used for the regulation of real and reactive powers of the converter. In the islanded mode of operation, the converter is controlled in the voltage-controlled mode. This paper deals with the modeling of both control schemes. Furthermore, reconnection from the islanded mode to the grid-connected mode based on the use of adequate Phase-Locked Loops (PLLs) has been demonstrated  

    Processing of symmetrical components in time-domain

    , Article IEEE Transactions on Power Systems ; Volume 22, Issue 2 , 2007 , Pages 572-579 ; 08858950 (ISSN) Karimi Ghartemani, M ; Karimi, H ; Sharif University of Technology
    2007
    Abstract
    A novel system for decomposing a set of three-phase signals into its constituting symmetrical components is proposed. The system also estimates the frequency, the magnitudes and phase-angles of the sequence components. The system is useful for online estimation of instantaneous symmetrical components and their attributes in the presence of frequency variations. The proposed system can be considered as a fundamentally improved version of the conventional three-phase Phase-Locked Loop (PLL) system which is widely used in power system applications. From this viewpoint, the proposed system obviates the inherent shortcoming of the conventional PLL system which is its erroneous response in the... 

    A low-power, second-order Δ/∑ modulator using a single class-AB op-amp for voice-band applications

    , Article Analog Integrated Circuits and Signal Processing ; Volume 49, Issue 2 , 2006 , Pages 199-211 ; 09251030 (ISSN) Safarian, A ; Sahandiesfanjani, F ; Heydari, P ; Atarodi, S. M ; Sharif University of Technology
    2006
    Abstract
    The design of a power-efficient second-order Δ/∑ modulator for voice-band is presented. At system level, a new single-loop, single-stage modulator is proposed. The modulator employs only one class-AB op-amp to realize a second-order noise shaping for voice-band applications. The modulator is designed in a 0.25μm standard CMOS process, and exhibits 86 dB dynamic range (DR) for a 4 kHz voice-bandwidth. The proposed modulator consumes 125μW from a 2.5 V supply. © Springer Science + Business Media, LLC 2006  

    A 1/4 rate linear phase detector for PLL-based CDR circuits

    , Article ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, Kos, 21 May 2006 through 24 May 2006 ; 2006 , Pages 3281-3284 ; 02714310 (ISSN); 0780393902 (ISBN); 9780780393905 (ISBN) Saffari, M ; Atarodi, M ; Tajalli, A ; Sharif University of Technology
    2006
    Abstract
    In this paper, a new 1/4 rate clock linear phase detector (PD) structure for PLL-based clock and data recovery (CDR) circuits will be suggested. The proposed topology offers a more suitable PD for high speed applications compared to the conventional topologies. The effect of duty cycle variation on the operation of CDR has been also studied. Designed in a 0.18μm CMOS technology, the proposed PD consumes 16mA from a 1.8V voltage supply. © 2006 IEEE  

    Almost zero-jitter optical clock recovery using all-optical kerr shutter switching techniques

    , Article Journal of Lightwave Technology ; Volume 33, Issue 9 , February , 2015 , Pages 1737-1747 ; 07338724 (ISSN) Damani, R ; Salehi, J. A ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    In this paper, a new all optical phase-locked loop (OPLL) is proposed and analyzed. The scheme relies on using two optical Kerr shutters to reveal the OPLL's error signal. The set of optical Kerr shutters and the subsequent low-speed photodetectors realize two nonlinear cross-correlations between the local clock pulse stream (called pump in Kerr shutter notations) and the time-shifted replicas of the incoming received data signal (called probe). The outputs of the cross-correlators are subtracted to form the error signal of the OPLL. We characterize the mathematical structure of the proposed OPLL and identify its two intrinsic sources of phase noise, namely, randomness of the received... 

    Micro-grid stabilizer design using sliding mode controller

    , Article International Journal of Electrical Power and Energy Systems ; Volume 116 , March , 2020 Mousavi Somarin, H ; Parvari, R ; Sharif University of Technology
    Elsevier Ltd  2020
    Abstract
    Future of the network stability is endangered by increasing the number of Distributed Generation (DG) and Renewable Energy Source (RES) units. The idea of the Virtual Synchronous Machine (VSM) has been raised to control the power electronic-based DG/RES converters in order to have better integration with the grid. This paper introduces a new stabilizer design for VSM-based converters to guarantee the stability of the micro-grid (MG). In this regard, the Sliding Mode Control (SMC) theory, which is robust against the disturbances and uncertainties, is employed to cope with the intermittent and nonlinear nature of DGs. The mutual operation of the proposed inverter and MG stabilizer has the... 

    Time to Digital Converters for ADPLL Applications

    , Ph.D. Dissertation Sharif University of Technology Molaei, Hasan (Author) ; Hajsadeghi, Khosrow (Supervisor)
    Abstract
    Effect of resolution of Time to Digital Converters (TDCs) on the performance of All-Digital Phase Locked Loops (ADPLLs) and capability of achieving higher resolution in advanced technologies lead to introducing different kinds of TDCs. Beside the analysis of different kinds of TDCs, This thesis proposes three new TDCs based on the time amplifi-cation concept. A new pipeline TDC is designed using a wide dynamic range time amplifi-er. A new method is used to widen dynamic range of the conventional time amplifiers. In order to get a low power high resolution conversion, a new delay element design is devel-oped to reduce the delay value and its sensitivity to mismatch and process variations.... 

    Low power Clock and Data Recovery Circuits in 20Gb/s Range in CMOS Technology

    , M.Sc. Thesis Sharif University of Technology Parkalian, Nina (Author) ; Hajsadeghi, Khosrow (Supervisor)
    Abstract
    Growing demand for increased data transmission in communication systems and the internet, has intensified the need to increase the bandwidth of high speed transceivers. One of the main elements in high speed receivers is the clock and data recovery circuit which guarantees the transfer of data with high reliability. In this thesis, the design of a clock and data recovery circuit for high frequency applications is considered. The aim of this project is the design of a circuit with low power and low jitter for high-speed input data. A new four stage LC ring oscillator is designed that works at the quarter rate of the input. A new idea for the design of the binary phase detectors has also been... 

    TDC & MMD Design for Bluetooth Low Energy Standard Transmitter

    , M.Sc. Thesis Sharif University of Technology Ghadami, Omid (Author) ; Fotowwat Ahmadi, Ali (Supervisor)
    Abstract
    IoE devices are going to integrate with our environment. It has been predicted that there would be more than 6 connected devices per each person by 2020. Currently what obstruct this technology from continuing its evolusion path, is its dependence on Ultra Low-Power devices, and for this reason there is a huge concenteration on Radio-Frequency standards which can make devices more power efficient. Within these standards, Bluetooth Low Energy (BLE) attracted designers consentration for its similarities with conventional Bluetooth and its dominance in cellphones and other portable devices.In this project, we have attempted to design a trasmitter for BLE standard based on an All Digital Phase... 

    Design, Fabrication and Analysis of Fast Wideband Frequency Synthesizer with Low Spurious and Phase Noise

    , M.Sc. Thesis Sharif University of Technology Vahedi, Pouria (Author) ; Banayi, Ali (Supervisor)
    Abstract
    In this thesis, design and fabrication of wide band frequency synthesizer with low spurious and low phase noise is investigted. It is very important to use an apropriate frequency synthesizer structure which would meet intended properties. In order to reach a low step size and high switching speed, using DDS is recomended; as well as using composition of DDS and PLL in order to meet a low spurious level. The main objective of this thesis is to investigate the best composition of outlet spures; so beside optimization of other properties, the main motivation has been focused on decreasing spures. Moreover, after studying Mechanisms of spures production in DDS outlet, some methods for... 

    Radio Receiver Design for Cognitive Radio in The UHF Band

    , M.Sc. Thesis Sharif University of Technology Nikoofard, Ali (Author) ; Fotowat Ahmady, Ali (Supervisor)
    Abstract
    With the ever-increasing communication need for propagating signals in authorized empty bands, the goal of this thesis is based on finding these unused bands and using them,which called Cognitive Radio. In this project, design and implementation of radio frequency building blocks of a receiver in the UHF band (400 to 800 MHz) is performed. In this project, however, the radio frequency building blocks include low noise amplifier, high-frequency quadrature mixers, high-frequency oscillators, tunable low-pass filter,band select filter,phase-locked loop and synthesizer, all of which are introduced, examined and implemented. Moreover, a new method which mitigates the speed limitation is verified....