Sharif Digital Repository

Phased array antennas are generally used for the inherent flexibility to beamforming and null-steering electronically. In the phased arrays the side lobes level (SLL) level is main problem which causes waste of energy or saturation of the receiver in the case of presence of the strong spatial blockers. In this paper, a weighting method was first used to reduce the level of SLL. However, this method increased the beam width and reduced resolution, which is not suitable for track applications. In next step hoping to increase the resolution, the distance between the antennas increased. But in this way, grating lobes appeared in the final beam. In fact, the main idea of the article is to solve... 

In the case that phased array systems are not capable of attenuating interferences, Radio Frequency (RF) front-ends and Analog Digital Converters (ADCs) with a large dynamic range are required to avoid saturation of the receiver. This leads to a higher power consumption. In this paper, employing N-path circuits in Mixer-First receivers, a novel method is introduced in which spatial and frequency blockers are eliminated right before entering the system on the antennas input. In fact using this technique, adjustable spatial notch filter and band-pass frequency filter are implemented to suppress spatial and frequency interferences. The proposed method enhances the robustness and effectiveness... 

In this letter, we use G/T as a figure of merit to evaluate the performance of time-modulated arrays (TMA). The noise performance of a receiver, which is periodically switched on and off, is quite different from that of a conventional receiver. We analytically investigate the noise performance of a TMA. Based on this analysis, the figure of merit, G/T, of the TMA structure is investigated, including the details of the receiver hardware. Moreover, the G/T of the TMA is compared with that of a phased array. The comparison indicates that the TMA structure provides the same or even better performance compared to a phased array system, which demonstrates the capability of TMA in providing... 

This paper presents a new implementation of adaptive beamforming algorithm that can be fully implemented on chip. It does not require the knowledge of the incoming signal direction or phase shifter characteristics. Besides, it eliminates the need for the ADC to convert the analog output signal to digital values for the microprocessor and the DAC to apply the calculated values to the control voltages of the analog phase shifters. Thus, it exhibits better convergence speed. In addition, the need for the complex and power-hungry processor is eliminated. Therefore, this implementation consumes less power. Analytical equations and constraints on system design parameters are derived, and the... 

This paper presents a new implementation of adaptive beamforming algorithm that can be fully implemented on chip. It does not require the knowledge of the incoming signal direction or phase shifter characteristics. Besides, it eliminates the need for the ADC to convert the analog output signal to digital values for the microprocessor and the DAC to apply the calculated values to the control voltages of the analog phase shifters. Thus, it exhibits better convergence speed. In addition, the need for the complex and power-hungry processor is eliminated. Therefore, this implementation consumes less power. Analytical equations and constraints on system design parameters are derived, and the... 

A 6-bit passive phase shifter for 2.5- to 3.2-GHz frequency band has been designed and implemented in a standard 0.18- μm CMOS technology. A new switched-network topology has been proposed for implementing the 5.625 ° phase shift step. The insertion loss of the circuit is compensated with an on-chip bidirectional amplifier. The measured return losses of the circuit are better than 8 dB with output 1-dB compression point of +9.5 dBm in the transmit mode and noise figure of 7.1 dB in the receive mode. The fabricated phase shifter demonstrates an average rms phase error of less than 2° over the entire operation bandwidth, which makes it suitable for high-precision applications  

This paper presents a highly-linear transceiver core chip for X-band phased-array systems with two RX and one TX channels. Implemented in a standard 0.18-μm CMOS technology, the core chip provides 6-bit phase control (with rms error <2°) and 6-bit gain control (with rms error <0.6 dB) both within the 8.5–11.5 GHz frequency band. Improved accuracy is also available by digital calibration in narrowband applications. The receivers achieve a gain of 13.5 dB, an IIP3 of +10.3 dBm, and a noise figure of 8.2 dB, while drawing 170 mA per channel from the 3.3 V supply. The chip also provides an additional low-gain mode which further enhances IIP3 to +19.1 dBm and the input-referred P1dB to +11.4 dBm....