Loading...
Search for:
pipeline-analog-to-digital-converters
0.006 seconds
A 1.5 v high-speed class AB operational amplifier for high-resolution high-speed pipelined A/D converters
, Article Proceedings of the 2003 IEEE International Symposium on Circuits and Systems, Bangkok, 25 May 2003 through 28 May 2003 ; Volume 1 , 2003 , Pages I273-I276 ; 02714310 (ISSN) ; Aslanzadeh, H. A ; Vahidfar, M. B ; Atarodi, M ; Sharif University of Technology
2003
Abstract
A low voltage high speed class AB op-amp with new structure is presented. The proposed op-amp has been designed to drive a large capacitive load as large as 10 pf dedicated for high-resolution high-speed pipelined analog to digital converters. Consuming comparatively low power about 6 mw, the proposed class AB op-amps has an output swing of 2.6 Vpp from a single supply of 1.5 volt. It has been observed that this op-amp can be suitable for a 1.5 volt 13-bit Pipelined A/D with sampling rate of 60 MS/S. This op-amp is to be fabricated in standard 0.18u CMOS technology
A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "slew boost" technique
, Article Proceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03), Seoul, 25 August 2003 through 27 August 2003 ; 2003 , Pages 340-344 ; 15334678 (ISSN) ; Mehrmanesh, S ; Vahidfar, M. B ; Safarian, A. Q ; Lotfi, R ; Sharif University of Technology
Association for Computing Machinery
2003
Abstract
An ultra-low-voltage low-power high-speed class-AB operational amplifier with a new structure is presented. A new technique called "Slew Boost" is introduced to improve amplifier's large-signal settling behavior, most useful in switched-capacitor circuits such as pipelined ADCs, sigma delta modulators, etc. The proposed op-amp has been designed to be employed in the first stage of a 10bit 150MSamples/sec pipelined analog-to-digital converter. Simulation results of the proposed fully-differential class-AB op-amp using 0.18um CMOS process models, confirm that it has an output swing of 1.5 Vp-p and consumes less than 1mW from a single supply of 1 volt
INL prediction method in pipeline ADCs
, Article APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 4 December 2006 through 6 December 2006 ; 2006 , Pages 13-16 ; 1424403871 (ISBN); 9781424403875 (ISBN) ; Sedighi, B ; Bakhtiar, M. S ; Sharif University of Technology
2006
Abstract
In this paper a general method for system level prediction of INL in pipeline analog to digital converters is presented. For each stage of the ADC, a new error model consisting of an input referred gain error and a nonlinear term is introduced. An analytic method to calculate INL from all error sources is presented. INL model for a switched-capacitor implementation is also presented. ©2006 IEEE
Yield constrained automated design algorithm for power optimized pipeline ADC
, Article Integration ; Volume 74 , 2020 , Pages 55-62 ; Sadrafshari, S ; Sharifkhani, M ; Sharif University of Technology
Elsevier B.V
2020
Abstract
Pipeline Analog to Digital Converter (ADC) design processes include several redesign steps to achieve the optimum solution. Hence, designers prefer to use automated algorithms for this purpose. In this paper, an automated algorithm for CAD tool is presented considering the trade-off between yield and power consumption for pipeline ADCs. This automated algorithm benefits from multiple degrees of freedom including the system level down to transistor level parameters, which helps CAD tools to find the optimized solution. It allows designers to choose an optimum scenario considering the trade-off between yield and power consumption. To evaluate the capabilities of this algorithm, a 10-bit...