Sharif Digital Repository

A new switching method for the stabilisation of a one-dimensional capacitor array tank for the stepwise charging of a load capacitor is presented. In this method, the tank capacitor configuration is rearranged in a circular manner once the charging process of a load capacitor finishes and before the charging process of a new load capacitor begins. Unlike previously reported methods, this method does not require backward switching for the stabilisation of tank capacitor voltages. Hence, the proposed method reduces the number of charging process steps by a factor of up to 2 compared with the conventional method. Moreover, since the tank recycles its charge inherently, the capacitive load can... 

A new nonlinear Time to Digital Converter (TDC) based on time difference amplification is the proposed. A new gain compensation method is presented to expand the DR of conventional × 2 Time Amplifiers (TAs). Instead of conventional gain compensation approach based on changing strength of current sources, the proposed technique uses current difference which results more stable gain over wider DR. In order to avoid two different paths of the stages, a sign bit detection part is the proposed at the front of the TDC to allow using one path of stages for both positive and negative input time differences. As a result, the most advantages of the proposed TDC are its high resolution, wide DR, and... 

A new low-power current reuse topology is proposed for the GPS receiver's RF front-end that combines the higher conversion gain and suppressed noise figure characteristics of cascade structures with the low power consumption of stacked architectures. The presented circuit, called 1.5-stage LMV cell, consists of LNA, Mixer and VCO (LMV) in such a formation that boosts LNA gain and suppresses mixer's noise figure by cascading the two stages while reusing their currents in the two stacked quadrature VCOs and placing the mixer's upper tree switches at the vicinity of on-off regions. The circuit is designed and its layout is generated in TSMC 0.18μm CMOS technology. Post-layout simulations using... 

A systematic approach to I/Q mismatch calibration in image-reject receivers is presented in this paper. A new error detection algorithm is proposed, which automatically calibrates for phase and gain mismatches limiting the performance of image-reject receivers. A dual-loop feedback is employed which looks for the minimum phase/gain error using a 2-dimensional analog-based search algorithm and then finds the minimum value for the error. An experimental CMOS prototype RF front-end for cognitive radio applications operating at 400-800 MHz is proposed and simulated in the 0.18 μm CMOS technology, achieving an image rejection ratio (IRR) better than 55-dB in post-layout simulation. The... 

A new switched-capacitor digital to analog converter (DAC) is presented. In this DAC, a ladder of series capacitors is used to generate the output voltage levels. A correction phase is used to increase the precision of the DAC. It is analytically shown that the proposed DAC is mismatch independent by virtue of the correction phase. That is after few correction phases (typically one), the effect of mismatch on the reference voltage levels on the ladder diminishes and an accurate voltage division is provided. It is proven that the whole process sinks no extra charge from the power supply. Furthermore, post layout simulations in 0.18 μm technology proves the benefits of the proposed method  

The fast growth of battery operated devices has made low power SRAM designs a necessity in recent years. Moreover, embedded SRAM units have become an important block in modern SoCs. The SRAM performance is limited by the cell stability during different operation. By adding extra transistor to the conventional 6T-cell, hold, read and write static noise margin (SNM) can be improved in the sub-threshold SRAM. In this paper we proposed a new 9T-cell SRAM that shows 80% and 50% improvement in read and write SNM respectively in comparison to the conventional 6T-cell SRAM. Using stack transistors in the leakage current path, the new structure shows lower bitline leakage assisting the sense... 

In this paper, a method is presented to reduce the power consumption of the two-stage dynamic comparators. In the two-stage dynamic comparators, the first stage (pre-amplifier stage) amplifies the input differential voltage. Then the second stage (latch stage) is activated and finishes the comparison. When the comparison is about to finish, the balance of the positive feedback of the latch stage tends to tilt toward one of the outputs; after this, to the end of the comparison, there is no need for additional pre-amplification gain which causes excess power consumption. In this paper, a method is proposed to eliminate this part of power consumption. It is shown that while reducing the power... 

A new low-power switching procedure for stepwise capacitor chargers is presented. In this procedure, a novel displacement method is utilized to improve the speed by a factor of two while preserving energy efficiency. Moreover, the load capacitor retains its charge after the charging process finishes and permits the circuit charge another predischarged load capacitor without an efficiency degradation problem (instability). Also, the control circuit of the switching procedure is implemented using only flip-flops with no combinational logic, therefore, it systematically prevents glitch power dissipation and improves the efficiency. Analytical derivations are proposed to model the switching... 

A state-of-the-art low-noise transimpedance amplifier (TIA) for 2.5 Gb/s family is presented using IBM 0.13-m CMOS technology. This TIA would be a part of a homodyne detector in a quantum key distribution (QKD) system. In this work a thorough design methodology based on a novel analytical noise optimization is presented. Also a unique method for eliminating the DC current of the input photodiodes (PDs) is proposed. The post-layout simulation results show bandwidth of 52 kHz to 1.9 GHz, average input referred noise of 1.93 pA/√Hz, and transimpedance gain of 80 db while dissipating 12 mW from a 1.5 V power supply, including the output buffer  

An analytical method is presented to characterize stepwise adiabatic circuits (SACs). In this method, the SACs are modeled as a discrete time system. Unlike previous methods, the stability is verified for arbitrary load capacitor ratios. Moreover, this method presents analytical derivations to offer an area/energy efficient design methodology. MATLAB simulations, post-layout simulations in the CMOS 0.18 μm technology, silicon measurements, and measurements based on discrete components confirm the precision of the analytical derivations. Using the proposed design methodology, a capacitive tank has been designed which reduces the energy consumption by 20% while the total size of the tank... 

A new low-power switching procedure for stepwise capacitor chargers is presented. In this procedure, a novel displacement method is utilized to improve the speed by a factor of two while preserving energy efficiency. Moreover, the load capacitor retains its charge after the charging process finishes and permits the circuit charge another predischarged load capacitor without an efficiency degradation problem (instability). Also, the control circuit of the switching procedure is implemented using only flip-flops with no combinational logic, therefore, it systematically prevents glitch power dissipation and improves the efficiency. Analytical derivations are proposed to model the switching... 

A low-power high-speed two-stage dynamic comparator is presented. In this circuit, the voltage swing of the first stage of the comparator, pre-amplifier stage, is limited to Vdd/2 in order to reduce the first stage power consumption. Also, this voltage swing limitation provides a strong drive at the evaluation phase for the second stage to enhance the comparison speed. Analytical derivations along with post layout simulation results prove that the proposed method speeds up the conventional circuit by a factor of two in the same budget of power consumption and offset voltage. Furthermore, the proposed circuit offers a wide input common mode range as large as the supply voltage while employing... 

A novel method of transmitter (TX) leakage cancellation is presented to improve the dynamic range of the receiver for wideband code division multiple access applications. The large TX leakage is attenuated within the low noise amplifier (LNA) output using a feed-forward path without any LNA noise figure degradation. A prototype has been designed and laid out in 0.18 μm CMOS technology. It achieves a maximum TX rejection of 18.5 dB with only 5.2 mA current consumption from 1.8 V supply voltage. LNA P-1dBCP (1 dB gain compression point) against TX leakage improves by more than 10 dB. Post layout simulations verify these results. Proposed structure dispels the requirement of off-chip surface... 

An active switched-capacitor 4-path bandpass filter suitable for multi-standard applications in ultra-high frequency (UHF) band with different channel bandwidths is designed and simulated in 0.18 μm CMOS technology. The baseband impedance of the filter is implemented as a second-order Gm-C low-pass filter which can be used to tune the channel bandwidth as well as the quality factor (Q) of the RF filter. The center frequency of the filter can be tuned from 100 MHz up to 1.5 GHz by changing the clock frequency applied to the filter while its bandwidth can be tuned by tuning impedance parameters in any center frequency. To do so, the baseband impedance utilizes a frequency dependent negative... 

A novel structure of Capacitive Digital to Analog Converters (CDAC) for Successive Approximation Register Analog to Digital Converters (SAR ADC) is presented. In this CDAC, a number of pre-charged capacitors are placed in different series configurations to produce a desired voltage level. Therefore, given an input code, a series configuration of the capacitors is created to produce a voltage. Current is drawn from the supply voltage only in one step of the ADC conversion to reduce the power consumption. Therefore, the proposed CDAC consumes a fixed and small amount of power regardless of the input code. The output common mode voltage (Vcm) of the DAC remains fixed for all the digital codes.... 

A low-power technique for high-resolution comparators is introduced. In this technique, p-type metal-oxide-semiconductor field-effect transistors are employed as the input of the latch of the comparator just like the input of the preamplifier. The latch and preamplifier stages are activated in a special pattern using an inverter-based controller. Unlike the conventional comparator, the preamplification delay can be set to an optimum low value even if after the preamplification, the output voltages is less than n-channel metal-oxide semiconductor voltage threshold. As a result, the proposed comparator reduces the power consumption significantly and enhances the speed. The speed and power... 

A large-signal linearization method for operational transconductance amplifiers (OTA) using a combination of cross-coupled quadratic cell and a novel non-linear current injection technique is presented in this paper. Post-layout simulations show that for 180 nm CMOS process with a 1.8 V power supply, total harmonic distortion (THD) at 1.5 V peak-to-peak and 5 kHz input is less than −46 dB. Also, the dynamic range (DR) at given THD is 68 dB with power consumption of 0.64 mW. To verify the performance, the proposed OTA is used to design a new configurable filter in high-frequency range using N-path filter methodology. Universal Butterworth Gm-C active filters are embedded in the proposed... 

In this paper, an adaptive design methodology for synthesizing a harmonic free N-path filter with reduced frequency folding is presented. System level analysis of proposed architecture shows that by adding a few extra paths with proper weights to a conventional N-path filter, several characteristics such as harmonic rejection, power reduction, foldback elimination and spectrum shaping can be achieved. The designed filter is reconfigurable to be a band-pass filter (BPF) or a band-reject filter (notch), based on the requirements. By using the nth harmonic of Local Oscillator (LO) signal, instead of the fundamental harmonic, the required input clock frequency in N-phase clock generator is...