Sharif Digital Repository

This paper proposes a low-cost fault-tolerant Carry Look-Ahead (CLA) adder which consumes much less power and area overheads in comparison with other fault-tolerant CLA adders. Analytical and experimental results show that this adder corrects all single-bit and multiple-bit transient faults. The Power-Delay Product (PDP) and area overheads of this technique are decreased at least 82% and 71%, respectively, as compared to adders which use traditional TMR, parity prediction, and duplication techniques. © 2009 IEEE  

Combination of three-dimensional (3D) IC technology and network on chip (NoC) is an effective solution to increase system scalability and also alleviate the interconnect problem in large-scale integrated circuits. However, because of the increased power density in 3D NoC systems and the destructive effect of high temperatures on chip reliability, applying thermal management solutions becomes crucial in such circuits. In this study, the authors propose a runtime distributed migration algorithm based on game theory to balance the heat dissipation among processing elements (PEs) in a 3D NoC chip multiprocessor. The objective of this algorithm is to minimise the 3D NoC system's peak temperature,... 

While the transistor density continues to grow exponentially in Field-Programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. This paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused Logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard Logic (GRHL) and a conventional... 

Promising advantages offered by resistive NonVolatile Memories (NVMs) have brought great attention to replace existing volatile memory technologies. While NVMs were primarily studied to be used in the memory hierarchy, they can also provide benefits in Field-Programmable Gate Arrays (FPGAs). One major limitation of employing NVMs in FPGAs is significant power and area overheads imposed by the Peripheral Circuitry (PC) of NVM configuration bits. In this paper, we investigate the applicability of different NVM technologies for configuration bits of FPGAs and propose a power-efficient reconfigurable architecture based on Phase Change Memory (PCM). The proposed PCM-based architecture has been... 

Combination of three-dimensional (3D) IC technology and network on chip (NoC) is an effective solution to increase system scalability and also alleviate the interconnect problem in large-scale integrated circuits. However, because of the increased power density in 3D NoC systems and the destructive effect of high temperatures on chip reliability, applying thermal management solutions becomes crucial in such circuits. In this study, the authors propose a runtime distributed migration algorithm based on game theory to balance the heat dissipation among processing elements (PEs) in a 3D NoC chip multiprocessor. The objective of this algorithm is to minimise the 3D NoC system's peak temperature,... 

The increasing trend in the number of smart connected devices has turned the routing procedure as one of the major challenges in IoT infrastructures. The Routing Protocol for Low Power and Lossy Networks (RPL) was introduced to satisfy different IoT application requirements through Objective Functions (OF). Although there have been several studies on introducing new OFs in order to fulfill specific IoT characteristics, e.g., energy and delay efficiency, reliability, and stability, but still there is a lack of novel OFs which fulfill the IoT application requirements in terms of both, the performance and the power consumption simultaneously. In this paper, we have proposed PEDAL, an OF which... 

The increasing trend in the number of smart connected devices has turned the routing procedure as one of the major challenges in IoT infrastructures. The Routing Protocol for Low Power and Lossy Networks (RPL) was introduced to satisfy different IoT application requirements through Objective Functions (OF). Although there have been several studies on introducing new OFs in order to fulfill specific IoT characteristics, e.g., energy and delay efficiency, reliability, and stability, but still there is a lack of novel OFs which fulfill the IoT application requirements in terms of both, the performance and the power consumption simultaneously. In this paper, we have proposed PEDAL, an OF which... 

Reliability and low power consumption are two major design objectives in today's embedded systems. Since floating-point units (FPU) are required for some embedded applications (e.g., multimedia applications), careful considerations should be given to the reliability and power consumptions of FPUs used in embedded systems. When using existing fault handling mechanisms for FPUs, it has been observed that the division operation imposes a considerable hardware overhead as compared to the addition, subtraction, and multiplication operations. Although the division operation is less frequently used, in reliable applications it is a must that all the components operate properly. In this paper, we... 

This paper proposes three ILP-based static thermalaware mapping algorithms for 3D Networks on Chip (NoC) to explore the thermal constraints and their effects on temperature and performance. Through complexity analysis, we show that the first algorithm, an optimal one, is not suitable for 3D NoC. Therefore, we develop two approximation algorithms and analyze their algorithmic complexities to show their proficiency. As the simulation results show, the mapping algorithms that employ direct thermal calculation to minimize the temperature reduce the peak temperature by up to 24% and 22%, for the benchmarks that have the highest communication rate and largest number of tasks, respectively. This... 

This paper proposes a Numeral-Based Crosstalk Avoidance Coding (NB-CAC) to protect communication channels of Network-on-Chips (NoCs) against crosstalk faults. The NB-CAC scheme produces codewords without bit patterns '101' and '010' to eliminate harmful transition patterns from NoC channels. This is done by the use of a new numeral system proposed in the paper. Using the proposed numeral system, the NB-CAC scheme 1) can be utilized in NoC channels with any arbitrary width, and 2) can be implemented with low area, power, and timing overheads. VHDL and SPICE simulations have been carried out for a wide range of channel widths to evaluate delay, area, and power consumption of the NB-CAC codecs.... 

The reliable transfer in Network on Chips (NoCs) can be threatened by crosstalk fault occurring in wires. Crossstalk fault is due to inter-wire coupling capacitance that based on the patterns of transitions appearing on the wires, significantly limits the reliability of NoCs. Among these transitions, 101 and 010 bit patterns impose the worst crosstalk effects to wires. This work intends to increase the reliability of NoCs against crosstalk faults by applying an improved Fibonacci-based numeral system, called Doubled-Penultimate Fibonacci (DP-Fibo). In the DP-Fibo coding algorithm, code words without ‘101’ and ‘010’ bit patterns are produced to reduce crosstalk faults. Experimental results... 

Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in Field-Programmable Gate Arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a single die, resulting in Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs). The architectures proposed in such studies inherently suffer from poor logic utilization which limits the benefits of power gating techniques. This paper proposes a Power-Efficient Architecture for FPGAs (PEAF) based on combination of... 

In this article, two soft error tolerant SRAM cells, the so-called RATF1 and RATF2, are proposed and evaluated. The proposed radiation hardened SRAM cells are capable of fully tolerating single event upsets (SEUs). Moreover, they show a high degree of robustness against single event multiple upsets (SEMUs). Over the previous SRAM cells, RATF1 and RATF2 offer lower area and power overhead. The Hspice simulation results through comparison with some prominent and state-of-the-art soft error tolerant SRAM cells show that our proposed robust SRAM cells have smaller area overhead (RAFT1 offers 58% smaller area than DICE), lower power delay product (RATF1 offers 231.33% and RATF2 offers 74.75%...