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Total 223 records

    Lazy instruction scheduling: Keeping performance, reducing power

    , Article ISLPED'08: 13th ACM/IEEE International Symposium on Low Power Electronics and Design, Bangalore, 11 August 2008 through 13 August 2008 ; 2008 , Pages 375-380 ; 15334678 (ISSN); 9781605581095 (ISBN) Mahjur, A ; Taghizadeh, M ; Jahangir, A. H ; Sharif University of Technology
    2008
    Abstract
    An important approach to reduce power dissipation is reducing the number of instructions executed by the processor. To achieve this goal, this paper introduces a novel instruction scheduling algorithm that executes an instruction only when its result is required by another instruction. In this manner, it not only does not execute useless instructions, but also reduces the number of instructions executed after a mispredicted branch. The cost of the extra hardware is 161 bytes for 128 instruction window size. Measurements done using SPEC CPU 2000 benchmarks show that the average number of executed instructions is reduced by 13.5% while the average IPC is not affected. Copyright 2008 ACM  

    Axiomatic design of step down DC/DC converter

    , Article 2008 IEEE International Conference on Industrial Technology, IEEE ICIT 2008, Chengdu, 21 April 2008 through 24 April 2008 ; 2008 ; 9781424417063 (ISBN) Kaboli, S ; Haddadi, A ; Khaligh, A ; Sharif University of Technology
    2008
    Abstract
    In this paper, the axiomatic design is introduced for designing the power electronic converters. The main idea of axiomatic design is to introduce variables affecting the desired performances of the system most independently possible. The design process is presented for a Buck converter. ©2008 IEEE  

    Axiomatic control of Buck converter for high efficiency over wide load range

    , Article 2008 IEEE International Conference on Industrial Technology, IEEE ICIT 2008, Chengdu, 21 April 2008 through 24 April 2008 ; 2008 ; 9781424417063 (ISBN) Kaboli, S ; Haddadi, A ; Khaligh, A ; Sharif University of Technology
    2008
    Abstract
    In this paper, the axiomatic design is introduced for controlling a power electronic converter. The main idea of axiomatic design is to introduce variables affecting the desired performances of the system most independently possible. The control process is presented for a Buck converter to achieve constant efficiency and output voltage ripple. ©2008 IEEE  

    Power flow control of a matrix converter based micro-turbine distributed generation system

    , Article 2006 IEEE Power Engineering Society General Meeting, PES, Montreal, QC, 18 June 2006 through 22 June 2006 ; 2006 ; 1424404932 (ISBN); 9781424404933 (ISBN) Nikkhajoei, H ; Karimi Ghartemani, M ; Sharif University of Technology
    IEEE Computer Society  2006
    Abstract
    This paper presents a power flow controller for a matrix converter as the power electronic interface between a high-speed micro-turbine generator and a utility distribution system. The matrix converter converts the high-frequency of a micro-turbine generator to a conventional frequency of the utility system, based on a novel switching strategy. The controller regulates magnitude and phase-angle of the converter output voltage to accommodate real and reactive power flow requirements of the utility system. Performance of the matrix converter based microturbine generation system including the power flow controller is evaluated based on digital time-domain simulation studies in the PSCAD/EMTDC... 

    High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement

    , Article Proceedings of the International Symposium on Low Power Electronics and Design ; 2011 , p. 79-84 ; ISSN: 15334678 ; ISBN: 9781612846590 Jadidi, A ; Arjomand, M ; Sarbazi-Azad, H ; Sharif University of Technology
    Abstract
    In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation. Therefore, the achieved cache... 

    Implementation and hardware in the loop verification of five-leg converter control system on a FPGA

    , Article IECON Proceedings (Industrial Electronics Conference), 7 November 2011 through 10 November 2011, Melbourne, VIC ; 2011 , Pages 4015-4020 ; 9781612849720 (ISBN) Shahbazi, M ; Zolghadri, M. R ; Poure, P ; Saadate, S ; Sharif University of Technology
    2011
    Abstract
    FPGAs are interesting choices for control of power electronics converters and electrical drives. In this paper, implementation of the control method of a reduced switch- count five-leg converter is carried out. Two PWM methods are studied. For verification of the implemented controller in a practical manner, without risking the damaging of the real system, "FPGA in the loop" experiments are performed. It is shown that using the proposed methodology, FPGA implementation and verification is fast and effective. The provided results show the high performance of the implemented controller on the FPGA, therefore the feasibility and suitability of the FPGA for this application is approved  

    High-endurance and performance-efficient design of hybrid cache architectures through adaptive line replacement

    , Article Proceedings of the International Symposium on Low Power Electronics and Design, 1 August 2011 through 3 August 2011 ; August , 2011 , Pages 79-84 ; 15334678 (ISSN) ; 9781612846590 (ISBN) Jadidi, A ; Arjomand, M ; SarbaziAzad, H ; Sharif University of Technology
    2011
    Abstract
    In this paper, we propose a run-time strategy for managing writes onto last level cache in chip multiprocessors where STT-RAM memory is used as baseline technology. To this end, we assume that each cache set is decomposed into limited SRAM lines and large number of STT-RAM lines. SRAM lines are target of frequently-written data and rarely-written or read-only ones are pushed into STT-RAM. As a novel contribution, a low-overhead, fully-hardware technique is utilized to detect write-intensive data blocks of working set and place them into SRAM lines while the remaining data blocks are candidates to be remapped onto STT-RAM blocks during system operation. Therefore, the achieved cache... 

    Active power filter control in three-phase four-wire systems using space vector modulation

    , Article 2006 International Conference on Power Electronics, Drives and Energy Systems, PEDES '06, New Delhi, 12 December 2006 through 15 December 2006 ; 2006 ; 078039772X (ISBN); 9780780397729 (ISBN) Mokhtari, H ; Rahimi, M ; Sharif University of Technology
    2006
    Abstract
    In this paper, by extending Space Vector Modulation (SVM) technique to three-phase four-wire systems, a new strategy is developed for the control of Active Power Filters (APFs). It is shown that the conventional SVM method cannot compensate for the current in the neutral wire in a three-phase four wire system. Simulations have been performed using PSCAD/EMTDC software. Simulation results are provided to prove the ability of the proposed technique in compensating the zero-sequence current. ©2006 IEEE  

    A high performance real-time simulator for controllers hardware-in-the-loop testing

    , Article Energies ; Volume 5, Issue 6 , 2012 , Pages 1713-1733 ; 19961073 (ISSN) Matar, M ; Karimi, H ; Etemadi, A ; Iravani, R ; Sharif University of Technology
    2012
    Abstract
    This paper presents a high performance real-time simulator for power electronic systems applications and primarily intended for controller hardware-in-the-loop (CHIL) testing. The novelty of the proposed simulator resides in the massively parallel hardware architecture that efficiently exploits fine-grained parallelism without imposing severe communication overhead time that can limit the performance. The simulator enables the use of a nanosecond range simulation timestep to simulate power electronic systems. Through the use of this nanosecond range simulation timestep, the simulator minimizes the error arising from the intersimulation timestep switching phenomenon associated with CHIL. The... 

    Optimal down sampling for ADC-based real-time simulation of basic power electronic converters

    , Article 8th Power Electronics, Drive Systems and Technologies Conference, PEDSTC 2017, 14 February 2017 through 16 February 2017 ; 2017 , Pages 259-264 ; 9781509057665 (ISBN) Rezayati, M ; Zolghadri, M. R ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2017
    Abstract
    In this paper, an optimal down sampler is used for Associate Discrete Circuit (ADC) based modeling and simulation of basic switching converters. Characteristic equation of backward Euler based discrete model of the circuit is used to find the value for down sampling. Using ADC modeling, fixed admittance matrix can be achieved for modeling switching converters and using down sampler, additional switch and diode current oscillations are minimized. Real-time digital simulation of buck converter using ADC with down sampler method is implemented on a Field Programmable Gate Array (FPGA) and the results are those expected without additional numerical oscillations. Based on the place-and-route... 

    Improvement of Power Sharing In Microgrids Consist of Synchronous Generators and Converter Based Distributed Generation Units

    , M.Sc. Thesis Sharif University of Technology Zanganeh, Mohsen (Author) ; Mokhtari, Hossein (Supervisor)
    Abstract
    This dissertation studies the operation of the power sharing system in a micro-grid (MG) which includes a synchronous generator and the converter based distributed generation (DG) units. Increasing advent of MGs and the huge penetration of DGs to the existing power systems require comprehensive studies on the interactions between synchronous generators and converter based DGs for the sharing of power during and after the occurrence of different disturbances such as load changing. Thus, this project discusses existing control methods which can be used to share the power between a synchronous generator and converter based DGs. Then, a new control strategy is proposed in order to enhance the... 

    Study Dynamic Behavior of Fuel Cell Distributed Generation

    , M.Sc. Thesis Sharif University of Technology Khojasteh, Meysam (Author) ; Abbaspour Tehrani Fard, Ali (Supervisor)
    Abstract
    The necessity of electrical energy, high cost of big power plants and high voltage transmission lines and also progressing of restructuring science has lead to the increasing of tendency to use the distributed generation in electrical industry. Among of different types of distributed generations, fuel cell power plants because of many advantages such as high efficiency, low emission, modular structure and ect., have a high potential to be used in power systems. The fuel cells produce electrical energy by chemical reactions. Due to the necessity of having the knowledge related to the chemical reaction which are effective on fuel cell, to study the fuel cell performance, this type of... 

    Control of a four-switch rectifier under unbalanced input voltage

    , Article PEDSTC 2014 - 5th Annual International Power Electronics, Drive Systems and Technologies Conference ; 2014 , p. 261-266 Ouni, S ; Javadian, V ; Shahbazi, M ; Zolghadri, M. R ; Sharif University of Technology
    Abstract
    Nowadays, reduced switch rectifiers are more interested because of less expense. Control of these rectifiers is an important part of their designing process. In this paper, a method is proposed for four-switch rectifier to continue working under unbalanced input voltage. To achieve this goal, first a method is introduced to separate positive and negative sequences of dq components. Also, the necessary condition is determined. Considering this condition, the control method is modified and new reference value for the control signals is calculated. Finally, the system is simulated in Simulink and the results are provided. These results confirm the accuracy of the developed model, and also the... 

    Speed control of a digital servo system using brain emotional learning based intelligent controller

    , Article PEDSTC 2013 - 4th Annual International Power Electronics, Drive Systems and Technologies Conference ; 2013 , Pages 311-314 ; 9781467344845 (ISBN) Jafari, M ; Shahri, A. M ; Shuraki, S. B ; Sharif University of Technology
    2013
    Abstract
    In this paper, a biologically motivated controller based on a mammalian limbic system called Brain Emotional Learning Based Intelligent Controller (BELBIC) is used for speed control of a Digital Servo System. The proposed controller is applied experimentally to a laboratory Digital Servo System 1 via MATLAB external mode. Comparing results of the proposed controller with conventional PID controller shows satisfactory performance including faster response and lower overshoot  

    Modeling, control and voltage unbalance compensation in a four-switch rectifier with input power factor correction

    , Article PEDSTC 2013 - 4th Annual International Power Electronics, Drive Systems and Technologies Conference ; 2013 , Pages 148-152 ; 9781467344845 (ISBN) Ouni, S ; Shahbazi, M ; Zolghadri, M ; Sharif University of Technology
    2013
    Abstract
    In this paper, a small signal model is proposed for four-switch rectifier with input power factor correction. The required transfer functions are determined and calculated for a typical rectifier. This model is used to design an appropriate controller with defined characteristic to improve the rectifier performance. Another controller is used to compensate capacitors dc voltage difference. The system is simulated in Simulink and the results are provided. These results confirm the accuracy of the developed model, and also the effectiveness of the proposed controllers  

    Analyzing and modeling of a new resonance inverter for low power vehicular application

    , Article PECon 2012 - 2012 IEEE International Conference on Power and Energy ; 2012 , Pages 576-581 ; 9781467350198 (ISBN) Mohagheghi, E ; Keipour, A ; Sudi, Z ; Moallemi, M ; Hajihosseinlu, A ; Sharif University of Technology
    2012
    Abstract
    In this paper we proposed a novel inverter to convert a DC voltage to a desired AC voltage. This inverter is designed for variable inductive loads and low output power applications. We proposed a novel simple PWM method which enables the inverter to keep the output current at six times more than the rated output current, without reducing output voltage value. In addition, based on a simple use of resonance in the circuit, the new inverter can raise the output voltage to extremely high amplitude for a relatively short time. These characteristics make the proposed inverter is useful for some industrial applications such as electrical vehicle. The new configuration of the circuit consists of a... 

    Output voltage quality intensification of diode clamped multilevel inverters using FM PWM technique

    , Article 2012 3rd Power Electronics and Drive Systems Technology, PEDSTC 2012, 15 February 2012 through 16 February 2012 ; February , 2012 , Pages 98-102 ; 9781467301114 (ISBN) Najmi, V ; Ebrahimi, S ; Oraee, H ; Sharif University of Technology
    2012
    Abstract
    Improvement in switching techniques is one of the effective methods for increasing the voltage quality in Multilevel Inverters. In this paper, a novel switching technique using frequency modulation is proposed to achieve high quality output voltage of multilevel inverters. This method is employed to different configurations of multilevel inverters consist of Diode Clamped (or Neutral Point Clamped), Flying Capacitor and Cascaded H-bridge. Each multilevel inverter which utilizes this technique is modeled and simulated to investigate the performance of this method by the help of MATLAB/Simulink software. The Results show that this innovative method considerably reduces total harmonic... 

    A combinational logic optimization for majority gate-based nanoelectronic circuits based on GA

    , Article 2011 International Semiconductor Device Research Symposium, ISDRS 2011, College Park, MD, 7 December 2011 through 9 December 2011 ; 2011 ; 9781457717550 (ISBN) Roohi, A ; Kamrani, M ; Sayedsalehi, S ; Navi, K ; Sharif University of Technology
    Abstract
    Quantum dots cellular automata is a new computing method in the nanotechnology that has considerable features such as low power, small dimension and high speed switch. A QCA device stores logic based on the position of individual electrons. The fundamental logic elements in QCA are the majority (Fig.1 (a)) and inverter gates (Fig.1 (b)) that operate based on the Coulomb repulsion between electrons [1]  

    Modeling, control and islanding detection of microgrids with passive loads

    , Article Proceedings of EPE-PEMC 2010 - 14th International Power Electronics and Motion Control Conference, 6 September 2010 through 8 September 2010 ; September , 2010 , Pages T11107-T11112 ; 9781424478545 (ISBN) Popov, M ; Karimi, H ; Nikkhajoei, H ; Terzija, V ; Sharif University of Technology
    2010
    Abstract
    This paper presents a control scheme for microgrids with passive loads. The existing control techniques for distributed generation systems are designed to operate either in the grid-connected or in the islanded mode. In the grid-connected mode of operation, a currentcontrolled scheme based on d-q variables is used for the regulation of real and reactive powers of the converter. In the islanded mode of operation, the converter is controlled in the voltage-controlled mode. This paper deals with the modeling of both control schemes. Furthermore, reconnection from the islanded mode to the grid-connected mode based on the use of adequate Phase-Locked Loops (PLLs) has been demonstrated  

    Dynamic model for Brushless Doubly-Fed Machine with stator winding faults

    , Article PEDSTC 2010 - 1st Power Electronics and Drive Systems and Technologies Conference, 17 February 2010 through 18 February 2010 ; February , 2010 , Pages 316-322 ; 9781424459728 (ISBN) Gorgin, H ; Sotoodeh, P ; Oraee, H ; Sharif University of Technology
    2010
    Abstract
    In this paper, a detailed analytical model for dynamic analysis of the Brushless Doubly-Fed Machine is presented. The model is capable to predict the machine behavior under different modes of operation including: simple induction mode, cascade mode and synchronous mode, both with and without winding faults and unbalanced excitations. The proposed approach employs the basic principles of the generalized harmonic theory for calculating self inductances and mutual inductances of circuits with any distribution of conductors. Dynamic equations of modified coupled-circuit method are then solved to compute the currents flowing in the stator windings and rotor loops