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    Higher-order four-wave mixing modeling in DWDM networks

    , Article Physica Scripta, Belgrade ; Volume T157 , 15 November , 2013 ; 02811847 (ISSN) Yazdani, A ; Noshad, M ; Sharif University of Technology
    2013
    Abstract
    In this paper, we derive a theoretical model for the higher-order four-wave mixing (FWM) power in wavelength division multiplexing networks with non-zero dispersion shifted fibers for the first time. We have investigated the higher-order FWM power theoretically and by numerical simulations. Dividing the fiber into a finite number of elements and applying the boundary conditions allow us to derive an expression for the second-order power penalty. At the end of each element, we derive the first-order FWM power for all wavelengths and use these values to calculate the second-order FWM power in the next element. Consequently, for each channel we can compute the total second-order FWM power... 

    Theoretical modeling and simulation of higher order FWM crosstalks in multichannel WDM optical communication systems

    , Article Advanced Materials Research, Xiamen ; Volume 660 , 2013 , Pages 130-134 ; 10226680 (ISSN) ; 9783037856413 (ISBN) Yazdani, A ; Noshad, M ; Farrokhi, A ; Sharif University of Technology
    2013
    Abstract
    In this paper, we derive a theoretical model for the higher order FWM power in WDM networks with NZDSF fibers for the first time. We have investigated the higher order FWM power theoretically and by numerical simulations. Dividing the fiber into finite number of elements and applying the boundary conditions, allow us derive an expression for second order power penalty. At the end of each element we derive the first order FWM power for all wavelengths and use these values to calculate the second order FWM power in the next element. Consequently, for each channel we can compute the total second order FWM power penalty at the end of the fiber  

    FPGA-based protection scheme against hardware trojan horse insertion using dummy logic

    , Article IEEE Embedded Systems Letters ; Volume 7, Issue 2 , 2015 , Pages 46-50 ; 19430663 (ISSN) Khaleghi, B ; Ahari, A ; Asadi, H ; Bayat-Sarmadi, S ; Sharif University of Technology
    Institute of Electrical and Electronics Engineers Inc  2015
    Abstract
    Hardware trojan horses (HTH) have recently emerged as a major security threat for field-programmable gate arrays (FPGAs). Previous studies to protect FPGAs against HTHs may still leave a considerable amount of logic resources to be misused by malicious attacks. This letter presents a low-level HTH protection scheme for FPGAs by filling the unused resources with the proposed dummy logic. In the proposed scheme, we identify the unused resources at the device layout-level and offer dummy logic cells for different resources. The proposed HTH protection scheme has been applied on Xilinx Virtex devices implementing a set of IWLS benchmarks. The results show that by employing the proposed HTH...