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process-variation
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Power reduction in HPC data centers: a joint server placement and chassis consolidation approach
, Article Journal of Supercomputing ; Vol. 70, issue. 2 , 2014 , p. 845-879 ; Momtazpour, M ; Goudarzi, M ; Sharif University of Technology
Abstract
Size and number of high-performance data centers are rapidly growing all around the world in recent years. The growth in the leakage power consumption of servers along with its exponential dependence on the ever increasing process variation in nanometer technologies has made it inevitable to move toward variation-aware power reduction strategies in data centers. In this paper, we address the problem of joint server placement and chassis consolidation to minimize power consumption of high-performance computing data centers under process variation. To this end, we introduce two variation-aware server placement heuristics as well as an integer linear programming (ILP)-based server placement...
Software-level instruction-cache leakage reduction using value-dependence of SRAM leakage in nanometer technologies
, Article Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) ; Volume 6590 , 2011 , Pages 275-299 ; 03029743 (ISSN); 9783642194474 (ISBN) ; Ishihara, T ; Noori, H ; Stenstrom P ; Sharif University of Technology
Abstract
Within-die process variation is increasing in nanometer-scale process technologies. We observe that the same SRAM cell leaks differently under within-die process variations when storing 0 compared to 1; this difference can be up to 3 orders of magnitude at 60mV variation of threshold voltage (V th). Thus, leakage can be reduced if most often the values that dissipate less leakage are stored in the cache SRAM cells. We take advantage of this fact to reduce instruction-cache leakage by presenting three binary-optimization and software-level techniques: we (i) reorder instructions within basic-blocks so that their bits better match the less-leaky state of their corresponding cache cells, (ii)...
Investigating the effects of process variations and system workloads on reliability of STT-RAM caches
, Article Proceedings - 2016 12th European Dependable Computing Conference, EDCC 2016, 5 September 2016 through 9 September 2016 ; 2016 , Pages 120-129 ; 9781509015825 (ISBN) ; Hosseini Monazzah, A. M ; Farbeh, H ; Miremadi, S. G ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2016
Abstract
In recent years, STT-RAMs have been proposed as a promising replacement for SRAMs in on-chip caches. Although STT-RAMs benefit from high-density, non-volatility, and low-power characteristics, high rates of read disturbances and write failures are the major reliability problems in STTRAM caches. These disturbance/failure rates are directly affected not only by workload behaviors, but also by process variations. Several studies characterized the reliability of STTRAM caches just for one cell, but vulnerability of STT-RAM caches cannot be directly derived from these models. This paper extrapolates the reliability characteristics of one STTRAM cell presented in previous studies to the...
Thermal- and Process-Variation-Aware Data Center Energy Reduction
, M.Sc. Thesis Sharif University of Technology ; Goudarzi, Maziar (Supervisor)
Abstract
Size and number of high-performance data centers are fast growing all over the world in recent years. The growth in the leakage power consumption of servers along with its exponential dependency on the ever increasing process variation in nanometer technologies have made it inevitable to move toward variation-aware power reduction strategies. In this thesis, we simultaneously apply thermal- and variation-aware server placement and chassis consolidation methods to reduce total power consumption of data centers. We introduce two server placement heuristics as well as an Integer Linear Programming (ILP)-based server placement method based on power consumption of each server and the data center...
Process Variation-Aware Task Scheduling for MPSoCs
,
Ph.D. Dissertation
Sharif University of Technology
;
Sanaei, Esmaeil
(Supervisor)
;
Goudarzi, Maziar
(Co-Advisor)
Abstract
Advances in semiconductor manufacturing technologies have enabled us to build billions of transistors on a single die. However, the increasing amount of process variation in nanometer technologies has made it inevitable to move toward statistical analysis methods, instead of deterministic worst-case-based techniques, at all design levels. In this project, we studied the problem of variation-aware task scheduling for MPSoCs. To this end, we first proposed a variability analysis framework to analyze the effect of process variation on the main parameters of MPSoCs. Then, to solve the MPSoC task scheduling problem, we proposed two metaheuristic variation-aware task scheduling method based on...
Statistical Analysis of Parameter Fluctuation on Performance of Giga Scale Integration
, M.Sc. Thesis Sharif University of Technology ; Sarvari, Reza (Supervisor)
Abstract
Developing to the sub-micron dimentions reduces the size of integrated circuits, so interconnects and a variations in their characteristics has more effects on circuit performance. Worst case study is the most common method in these systems, but in many cases interconnect lines are independent from eachother. Analysis state that worst case is out of the distribution in many cases (with zero possibility) and result in a pessimistic design. Statistical analysis should replace worst case analysis in multi varient systems. In this titile, statistical analysis will be used to investigate performance of interconnects in new technology. Maximum variation in interconnect parameters are considered...
Process-Variation-Aware Configuration Selection of Configurable MPSOC for Power-Yield Maximization
, M.Sc. Thesis Sharif University of Technology ; Goudarzi, Maziar (Supervisor)
Abstract
Process Variation is seen as statistical variations in leakage current and delay of transistors in nano-scale technologies. The amount of process variations increase as the size of transistors decrease by technology scaling such that those effects can be seen in frequency of MPSoC (Multi-Processor System-on-Chip) cores and their leakage power deviation. These variations cause the tasks duration and power consumption fluctuate in different processors in an MPSoC instance. Consequently, some chip instances of the same MPSoC may consume more time and power than their considered limitations. Hence considering the process variation is necessary and required for MPSoC optimization at different...
Leak-Gauge: A late-mode variability-aware leakage power estimation framework
, Article Microprocessors and Microsystems ; Volume 37, Issue 8 PARTA , 2013 , Pages 801-810 ; 01419331 (ISSN) ; Momtazpour, M ; Goudarzi, M ; Sharif University of Technology
2013
Abstract
Leakage power has already become the major contributor to the total on-chip power consumption, rendering its estimation a necessary step in the IC design flow. The problem is further exacerbated with the increasing uncertainty in the manufacturing process known as process variability. We develop a method to estimate the variation of leakage power in the presence of both intra-die and inter-die process variability. Various complicating issues of leakage prediction such as spatial correlation of process parameters, the effect of different input states of gates on the leakage, and DIBL and stack effects are taken into account while we model the simultaneous variability of the two most critical...
Low cost soft error hardened latch designs for nano-scale CMOS technology in presence of process variation
, Article Microelectronics Reliability ; Volume 53, Issue 6 , June , 2013 , Pages 912-924 ; 00262714 (ISSN) ; Tabandeh, M ; Fazeli, M ; Sharif University of Technology
2013
Abstract
In this paper, two Low cost and Soft Error Hardened latches (referred to as LSEH1 and LSEH2) are proposed and evaluated. The proposed latches are fully SEU immune, i.e. they are capable of tolerating all particle strikes to any of their nodes. Moreover, they can mask Single Event Transients (SETs) occurring in combinational logics and reaching the input of the latches. We have compared our SEU/SET-tolerant latches with some well-known previously proposed soft error tolerant latches. To evaluate the proposed latches, we have done a set of SPICE simulations. The simulation results trough comparisons with other hardened latches reveal that the proposed latches not only have more robustness but...
Variation-aware server placement and task assignment for data center power minimization
, Article Proceedings of the 2012 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2012 ; 2012 , Pages 158-165 ; 9780769547015 (ISBN) ; Momtazpour, M ; Goudarzi, M ; Sharif University of Technology
2012
Abstract
Size and number of data centers are fast growing all over the world and their increasing total power consumption is a worldwide concern. Moreover, increase in the amount of process variation in nanometer technologies and its effect on total power consumption of servers has made it inevitable to move toward variation-aware power reduction strategies. This paper formulates a variation-aware joint server placement and task assignment method using Integer Linear Programming (ILP) to minimize total power consumption of data centers. We first determine the optimum placement of servers in the data center racks based on total power consumption of each server and the data center recirculation model...
Simultaneous variation-aware architecture exploration and task scheduling for MPSoC energy minimization
, Article Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI ; 2011 , Pages 271-276 ; 9781450306676 (ISBN) ; Ghorbani, M ; Goudarzi, M ; Sanaei, E
Abstract
In nanometer-scale process technologies, the effects of process variations are observed in Multiprocessor System-on-Chips (MPSoC) in terms of variations in frequencies and leakage powers among the processors on the same chip as well as across different chips of the same design. Traditionally, worst-case values are assumed for these parameters and then a deterministic optimization technique is applied to the MPSoC application under design. We show that such worst-case-based approaches are not optimal with the increasing variation observed at system-level, and instead, statistical approaches should be employed. We consider the problem of simultaneously choosing MPSoC architecture and task...
Using intra-line level pairing for graceful degradation support in PCMs
, Article Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, 8 July 2015 through 10 July 2015 ; Volume 07-10-July-2015 , 2015 , Pages 527-532 ; 21593469 (ISSN) ; 9781479987184 (ISBN) ; Sarbazi Azad, H ; Sharif University of Technology
IEEE Computer Society
2015
Abstract
In Phase-Change Memory (PCM), the number of writes a cell can take before wearing-out is limited and highly varied due to unbalanced write traffic and process variation. After the failure of weak cells and in presence of large number of failed lines, some techniques have been proposed to further prolong the lifetime of a PCM device by remapping failed lines to spares and salvage a PCM device with graceful degradation. Others rely on handling failures through inter-line pairing. Observations reveal that most of cells in a line are healthy when the line is marked as faulty by any of these proposals. To overcome this deficiency, we propose Intra-line Level Pairing(ILP), a technique that...
Communication at the Speed of Light (CaSoL): A New Paradigm for Designing Global Wires
, Article IEEE Transactions on Electron Devices ; Volume 66, Issue 8 , 2019 , Pages 3466-3472 ; 00189383 (ISSN) ; Rassekh, A ; Shahhosseini, S ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
In this paper, we argue that communication at the speed of light (CaSoL) through on-chip copper interconnects is possible in the near future based on giga-scale integration (GSI) technologies. A three-step algorithm is introduced to design the optimum buffers in such systems. HSPICE simulations show that a 1.3× time of flight (TF) is reachable in 7-nm FinFET technology. It is also shown that such a design is by nature, robust, and immune to process variations and crosstalk noise. © 1963-2012 IEEE
Addressing issues with MLC phase-change memory
, Article Advances in Computers ; Volume 118 , 2020 , Pages 111-133 ; Sarbazi Azad, H ; Sharif University of Technology
Academic Press Inc
2020
Abstract
All of the presented solutions in this book focused on using MLC phase change memory (PCM) due to density advantage and prolonging PCM lifetime. However, resistance drift can be one of the challenging issues for MLC PCMs. While it is desired to have the density advantage of MLC, the trade-off is resistance drift. Since MLCs have closely separated resistance regions, drift has a chance of overlapping intermediate regions. It may then bring out either single bit or multi-bit soft error. Indeed, drift source is related to the semi amorphous resistance regions that are metastable vs time and temperature while crystalline resistance proves to be stable across time and temperature. This chapter...
Low-leakage soft error tolerant dual-port SRAM cells for cache memory applications
, Article Microelectronics Journal ; Volume 43, Issue 11 , November , 2012 , Pages 766-792 ; 00262692 (ISSN) ; Manzuri Shalmani, M. T ; Sharif University of Technology
2012
Abstract
As transistor dimensions are reduced due to technological advances, the area constraint is becoming less restrictive, but soft error rate, leakage current, and process variation are drastically increased. Therefore, in nano-scaled CMOS technology, soft error rate, leakage current and process variation are the most important issues in designing embedded cache memory. To overcome these challenges, and based on the observation that cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper deals with new low leakage, hardened, and read-static-noise-margin-free SRAM memory cells for nano-scaled CMOS technology. These cells are completely hardened and cannot...
A nanoscale CMOS SRAM cell for high speed applications
, Article 5th International Conference on MEMS NANO, and Smart Systems, ICMENS 2009, 28 December 2009 through 30 December 2009, Dubai ; 2010 , Pages 33-36 ; 9780769539386 (ISBN) ; Manzuri Shalmani, M. T ; Mehrparvar, A ; Sharif University of Technology
2010
Abstract
The leakage current and process variation are drastically increased with technology scaling. In Conventional SRAM cell due to process variations, stored data can be destroyed during read operation. Therefore, leakage current of SRAM cell and stability during read operation are two important parameters in nano-scaled CMOS technology. To overcome these limitations and to increase the speed of conventional SRAMs, we have developed a read-static-noise-margin-free SRAM cell. The developed cell has six-transistors and uses two read/write-lines and two read/write-bit-lines during read/write operation. This cell retains its data with leakage current and positive feedback without refresh cycle. The...
Run-time adaptive power-aware reliability management for many-cores
, Article IEEE Design and Test ; 2017 ; 21682356 (ISSN) ; Ejlali, A ; Shafique, M ; Sharif University of Technology
Abstract
Escalating reliability threats and performance issues due to process variations under the tight power envelopes of multi- /many-core chips challenge the cost-effective deployment of future technology nodes. We propose an adaptive run-time system that synergistically integrates heterogeneous hardening modes at both hardware and software levels, and selects appropriate hardening modes for concurrently executing applications under total chip power budget and timing constraints, while optimizing for reliability. To enable a high level of adaptability, we perform a comprehensive analysis of various design tradeoffs and study the impact of hardware/software hardening modes in terms of achieved...
Run-Time adaptive power-aware reliability management for manycores
, Article IEEE Design and Test ; Volume 35, Issue 5 , 2018 , Pages 36-44 ; 21682356 (ISSN) ; Ejlali, A ; Shafique, M ; Sharif University of Technology
IEEE Computer Society
2018
Abstract
Editor's note: Due to increasing process, voltage, and temperature (PVT) variability, reliability is becoming a growing worry. This article addresses this concern with a combination of software and hardware hardening modes while considering power, performance, and overhead constraints. Similar to other examples in this special issue, this work illustrates that complex management tasks that have to integrate multiple objectives, goals, and constraints require a comprehensive understanding of the system's state. - Axel Jantsch, TU Wien - Nikil Dutt, University of California at Irvine. © 2013 IEEE
A system-level framework for analytical and empirical reliability exploration of stt-mram caches
, Article IEEE Transactions on Reliability ; 2019 ; 00189529 (ISSN) ; Farbeh, H ; Asadi, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
Spin-transfer torque magnetic RAM (STT-MRAM) is known as the most promising replacement for static random access memory (SRAM) technology in large last-level cache memories (LLC). Despite its high density, nonvolatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAM-based cache memory suffers from high error rates mainly due to retention failure (RF), read disturbance, and write failure. Existing studies are limited to estimate the rate of only one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, whose estimation is a must to design cost-efficient reliable caches, has not been studied previously. In...
A system-level framework for analytical and empirical reliability exploration of stt-mram caches
, Article IEEE Transactions on Reliability ; 2019 ; 00189529 (ISSN) ; Farbeh, H ; Asadi, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2019
Abstract
Spin-transfer torque magnetic RAM (STT-MRAM) is known as the most promising replacement for static random access memory (SRAM) technology in large last-level cache memories (LLC). Despite its high density, nonvolatility, near-zero leakage power, and immunity to radiation as the major advantages, STT-MRAM-based cache memory suffers from high error rates mainly due to retention failure (RF), read disturbance, and write failure. Existing studies are limited to estimate the rate of only one or two of these error types for STT-MRAM cache. However, the overall vulnerability of STT-MRAM caches, whose estimation is a must to design cost-efficient reliable caches, has not been studied previously. In...