Sharif Digital Repository

The Graphics Processing Unit (GPU) is the most promising candidate platform for faster rate of improvement in peak processing speed, low latency and high performance. The highly programmable and multithreaded nature of GPUs makes them a remarkable candidate for general purpose computing. However, supporting non-graphics computing on graphics processors requires addressing several architecture challenges. In this paper, we focus on improving performance by better hiding long waiting time to transfer data from the slow global memory. Thereupon study an effective light-overhead prefetching mechanism, which utilizes idle processing elements. Our results show that we can potentially improve... 

The graphics processing unit (GPU) is the most promising candidate platform for achieving faster improvements in peak processing speed, low latency and high performance. The highly programmable and multithreaded nature of GPUs makes them a remarkable candidate for general purpose computing. However, supporting non-graphics computing on graphics processors requires addressing several architectural challenges. In this paper, we focus on improving performance by better hiding long waiting time for transferring data from the slow global memory. Furthermore, we show that the proposed method can reduce power and energy. Reduction in access time to off-chip data has a noticeable role in reducing... 

Multiprocessor systems have been widely used for the execution of parallel applications. Task scheduling is crucial for the right operation of multiprocessor systems, where the aim is shortening the length of schedules. Fault tolerance is becoming a necessary attribute in multiprocessor systems as the number of processing elements is getting larger. This paper presents a fault tolerant scheduling algorithm for task graph applications in multiprocessor systems. The algorithm is an extension of a previously proposed algorithm with a reduced communications scheme. Simulation results show the efficiency of the proposed algorithm despite its simplicity  

In this paper, a parallel algorithm is presented for data clustering on a multicomputer with star topology. This algorithm is fast and requires a small amount of memory per processing element, which makes it even suitable for SIMD implementation. The proposed parallel algorithm completes in O(K+S2-T2) steps for a clustering problem of N data patterns with M features per pattern and K clusters where S and T are the minimum numbers such that NM≤S! and KM≤T!, on the S-dimensional star graph  

In this paper, a parallel algorithm for data clustering is presented on a multi-computer with star topology. This algorithm is fast and requires a small amount of memory per processing element, which makes it even suitable for SIMD implementation. The proposed parallel algorithm completes in O(K+S 2-T 2) steps for a clustering problem of N data patterns with M features per pattern and K clusters, where N.M = S!, K.M = T!, and M=R!, on a s-star interconnection network. © Springer-Verlag Berlin Heidelberg 2005  

Combination of three-dimensional (3D) IC technology and network on chip (NoC) is an effective solution to increase system scalability and also alleviate the interconnect problem in large-scale integrated circuits. However, because of the increased power density in 3D NoC systems and the destructive effect of high temperatures on chip reliability, applying thermal management solutions becomes crucial in such circuits. In this study, the authors propose a runtime distributed migration algorithm based on game theory to balance the heat dissipation among processing elements (PEs) in a 3D NoC chip multiprocessor. The objective of this algorithm is to minimise the 3D NoC system's peak temperature,... 

Combination of three-dimensional (3D) IC technology and network on chip (NoC) is an effective solution to increase system scalability and also alleviate the interconnect problem in large-scale integrated circuits. However, because of the increased power density in 3D NoC systems and the destructive effect of high temperatures on chip reliability, applying thermal management solutions becomes crucial in such circuits. In this study, the authors propose a runtime distributed migration algorithm based on game theory to balance the heat dissipation among processing elements (PEs) in a 3D NoC chip multiprocessor. The objective of this algorithm is to minimise the 3D NoC system's peak temperature,... 

Phased array antennas are generally used for the inherent flexibility to beamforming and null-steering electronically. In the phased arrays the side lobes level (SLL) level is main problem which causes waste of energy or saturation of the receiver in the case of presence of the strong spatial blockers. In this paper, a weighting method was first used to reduce the level of SLL. However, this method increased the beam width and reduced resolution, which is not suitable for track applications. In next step hoping to increase the resolution, the distance between the antennas increased. But in this way, grating lobes appeared in the final beam. In fact, the main idea of the article is to solve... 

A distributed embedded system consists of different processing elements (PEs) communicating via communication links. PEs have various power characteristics and in turn, have different thermal profiles. With new technologies, processor power density is dramatically increased which results in high temperature. This alarming trend underscores the importance of temperature management methods in system design. The majority of proposed techniques to address thermal issues, impose severe penalties on performance and reliability. We present Schedule Swapping, a technique for reducing peak temperature in distributed embedded systems while satisfying real-time constraints. Contrary to many other... 

Fused CPU-GPU architectures that utilize the powerful features of both processors are common nowadays. Using homogeneous interconnect for such heterogeneous processors can result in performance degradation and power increase. This paper explores the optimization of heterogeneous NoC design to connect heterogeneous CPU-GPU architecture in terms of NoC performance and power. This involves solving four different NoC design sub-problems simultaneously; processing elements (PEs) mapping, buffer size and virtual channel assignments, and links' bandwidth determination. Heuristic-based optimization methods were proposed to obtain a near-optimal heterogeneous NoC design, and formal models were used...