Sharif Digital Repository

In this article, a design methodology is presented to realize integrated class-F high-power amplifiers (HPAs). A harmonic-control network (HCN) is proposed to present short- and open-circuit impedances to each transistor employed in the output stage of the HPA at {2}f {0} and {3}f {0} frequencies. The HCN absorbs the parasitic capacitance of the transistor and lends itself to be absorbed in the matching and power combiner networks, reducing the die area of the HPA. A proof-of-concept 9.7-10.3-GHz class-F HPA was designed and implemented in a 0.25- μ ext{m} GaAs pHEMT technology with V {DD} of 6 V. The designed HPA consists of two amplifying stages, and its output stage includes 16... 

In this article, a design methodology is presented to realize integrated class-F high-power amplifiers (HPAs). A harmonic-control network (HCN) is proposed to present short- and open-circuit impedances to each transistor employed in the output stage of the HPA at {2}f {0} and {3}f {0} frequencies. The HCN absorbs the parasitic capacitance of the transistor and lends itself to be absorbed in the matching and power combiner networks, reducing the die area of the HPA. A proof-of-concept 9.7-10.3-GHz class-F HPA was designed and implemented in a 0.25- μ ext{m} GaAs pHEMT technology with V {DD} of 6 V. The designed HPA consists of two amplifying stages, and its output stage includes 16... 

This paper presents a design procedure for a wideband 6-18-GHz monolithic microwave integrated circuit highpower amplifier (HPA) in 0.25-μm AlGaAs-InGaAs pHEMT technology. The design is mainly focused on the realization of the passive circuits to provide the required low-loss and wideband impedance transformation networks. The two-stage GaAs HPA achieves an average output power of 39.6 dBm and a peak output power of 40.5 dBm at 11 GHz, in pulsed mode operation, with a small-signal gain of S21 > 10 dB over the entire bandwidth. The average power added efficiency (PAE) is 22%, with a peak PAE of 29% at 11 GHz. The HPA chip occupies an area of 5×3.6 mm2. The achieved output power and the... 

In this article, a design methodology is presented to realize integrated class-F high-power amplifiers (HPAs). A harmonic-control network (HCN) is proposed to present short- and open-circuit impedances to each transistor employed in the output stage of the HPA at 2f_0 and 3f_0 frequencies. The HCN absorbs the parasitic capacitance of the transistor and lends itself to be absorbed in the matching and power combiner networks, reducing the die area of the HPA. A proof-of-concept 9.7-10.3-GHz class-F HPA was designed and implemented in a 0.25-μm GaAs pHEMT technology with VDD of 6 V. The designed HPA consists of two amplifying stages, and its output stage includes 16 transistors in parallel to...