Search for: read-performance
Article 2013 21st Iranian Conference on Electrical Engineering ; May , 2013 ; 9781467356343 (ISBN) ; Zamani, M ; Hajsadeghi, K ; Sharif University of Technology
The constraints of power saving have compelled SRAM designers to consider sub-threshold area as a viable choice. The biggest barrier of this progress is the stability of SRAM's cells and the correct operations. In this paper a 10T cell structure has been proposed with 90% read and 50% write SNM improvement in comparison to the conventional 6T cell. The hold SNM value is about the 6T cell SRAM. Also using differential read method in the proposed structure causes high read performance and using simpler sense amplifier. The symmetric configuration of this structure helps the SRAM has simpler layout and lower transistor mismatch. Using 90nm TSMC CMOS, 32kb 10T cell SRAM in sub-threshold area is...
Article ACM Transactions on Architecture and Code Optimization ; Volume 12, Issue 4 , January , 2015 ; 15443566 (ISSN) ; Arjomand, M ; Sarbazi Azad, H ; Sharif University of Technology
Association for Computing Machinery 2015
Phase Change Memory (PCM) devices are one of the known promising technologies to take the place of DRAM devices with the aim of overcoming the obstacles of reducing feature size and stopping ever growing amounts of leakage power. In exchange for providing high capacity, high density, and nonvolatility, PCM Multilevel Cells (MLCs) impose high write energy and long latency. Many techniques have been proposed to resolve these side effects. However, read performance issues are usually left behind the great importance of write latency, energy, and lifetime. In this article, we focus on read performance and improve the critical path latency of the main memory system. To this end, we exploit...
Article AEU - International Journal of Electronics and Communications ; Volume 99 , 2019 , Pages 361-368 ; 14348411 (ISSN) ; Moaiyeri, M. H ; Moghaddam, M ; Hessabi, S ; Sharif University of Technology
Elsevier GmbH 2019
This paper presents a single-ended low-power 7T SRAM cell in FinFET technology. This cell enhances read performance by isolating the storage node from the read path. Moreover, disconnecting the feedback path of the cross-coupled inverters during the write operation enhances WSNM by nearly 7.7X in comparison with the conventional 8T SRAM cell. By using only one bit-line, this cell reduces power consumption and PDP compared to the conventional 8T SRAM cell by 82% and 35%, respectively. © 2018 Elsevier GmbH