Sharif Digital Repository

Forthcoming networked systems require mechanisms for on-the-fiy reconfiguration in their protocol stacks to be able to operate in different situations and networks. Since every protocol in a protocol stack has at least one peer protocol in another system, dynamic reconfiguration of a protocol raises the need for reconfiguration in the peer stack. For an assured dynamic (run-time) reconfiguration, executions of two peer protocols are stopped in a safe state, new protocols are initialized, and stacks switch to the new protocols at the same time. This paper proposes a software framework for dynamic reconfiguration of two communicating protocol stacks. A distributed algorithm is implemented in... 

Following Moore's law, the number of transistors on chip has grown exponentially for decades. This growing transistor count, coupled with recent architecture and compiler advances, has resulted in an unprecedented exponential performance increase of computers. With the end of Dennard scaling, however, the power required to operate all transistors at the full performance level simultaneously grows across the technology generations. Consequently, chips will keep an increasing fraction of transistors power gated or dark to remain within the power envelope. The power-gated part of the chip, known as dark silicon, is expected to comprise a significant portion of the die real estate in new... 

With the increasing use of pervasive computing environments (PCEs), developing dynamic reconfigurable software in such environments becomes an important issue. The ability to change software components in running systems has advantages such as building adaptive, long-life, and self-reconfigurable software as well as increasing invisibility in PCEs. As dynamic reconfiguration is performed in error-prone wireless mobile systems frequently, it can threaten system safety. Therefore, a mechanism to support assured dynamic reconfiguration at run-time for PCEs is required. In this paper, we propose an Assured Dynamic Reconfiguration Framework (ADRF) with emphasis on assurance analysis. The... 

Due to the important role that distribution systems play in quality of power delivered to the customers, there has always been a great deal of interest in investigating different methods of efficiency enhancement for these networks. Two of these methods are Feeder Reconfiguration (FR) and Capacitor Allocation (CA); both have been widely employed to reduce losses and improve several other operational characteristics in electrical power distribution systems. As in FR process the topology of the network changes, it is necessary to change some previous settings; for instance: the capacity of capacitor banks in service in each bus, after each reconfiguration process. This is due to the fact that... 

Topology is widely known as the most important characteristic of networks-on-chip (NoC), since it highly affects overall network performance, cost, and power consumption. In this paper, we propose a reconfigurable architecture and design flow for NoCs on which a customized topology for any target application can be implemented. In this structure, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a mesh to benefit from the interesting characteristics of the mesh topology, i.e. regular structure and efficient handling of local traffic. A reconfigurable inter-cluster topology then eliminates the... 

Topology is widely known as the most important characteristic of networks-on-chip (NoC), since it highly affects overall network performance, cost, and power consumption. In this paper, we propose a reconfigurable architecture and design flow for NoCs on which a customized topology for any target application can be implemented. In this structure, the nodes are grouped into some clusters interconnected by a reconfigurable communication infrastructure. The nodes inside a cluster are connected by a mesh to benefit from the interesting characteristics of the mesh topology, i.e. regular structure and efficient handling of local traffic. A reconfigurable inter-cluster topology then eliminates the... 

The dynamic nature of today’s manufacturing industry, which is caused by the intense global competition and constant technological advancements, requires systems that are highly adaptive and responsive to demand fluctuations. Reconfigurable manufacturing systems (RMS) enable such responsiveness through their main characteristics. This paper addresses the problem of RMS configuration design, where the demand of a single product varies throughout its production life cycle, and the system configuration must change accordingly to satisfy the required demand with minimum cost. A two-phased method is developed to handle the primary system configuration design and the necessary system... 

Growing the need for long-life and high-available programs, dynamic reconfiguration is going to be an important research issue. Dynamic reconfiguration enables the software systems to change at runtime to decrease their down-time in case of any updating, upgrading or in any changes. Any invalid reconfiguration at runtime may lead programs into invalid states. In this paper, we investigate on validity of dynamic reconfiguration for component-based programs and propose validity conditions for it. We show that the problem of validity assurance in general is undecidable and there is no general-purpose algorithm to verify dynamic reconfiguration validity. To have a computable algorithm for... 

High availability of software systems is an essential requirement for pervasive computing environments. In such systems self-adaptation, using dynamic reconfiguration is also a key feature. However, dynamic reconfiguration potentially decreases the system availability by making parts of the system temporary frozen, especially during incomplete or faulty execution of the reconfiguration process. In this paper, we propose Assured Dynamic Reconfiguration Framework (ADRF), consisting of run-time analysis phases, assuring the desired correctness and completeness of dynamic reconfiguration process. We also specify factors that affect availability of reconfigurable software in pervasive computing... 

While the transistor density continues to grow exponentially in Field-Programmable Gate Arrays (FPGAs), the increased leakage current of CMOS transistors act as a power wall for the aggressive integration of transistors in a single die. One recently trend to alleviate the power wall in FPGAs is to turn off inactive regions of the silicon die, referred to as dark silicon. This paper presents a reconfigurable architecture to enable effective fine-grained power gating of unused Logic Blocks (LBs) in FPGAs. In the proposed architecture, the traditional soft logic is replaced with Mega Cells (MCs), each consists of a set of complementary Generic Reconfigurable Hard Logic (GRHL) and a conventional... 

Despite widespread use of SRAM-based reconfigurable devices (SRDs) in mainstream applications, their usage has been very limited in enterprise and safety-critical applications due to SRAM susceptibility to soft errors. Previous mitigation techniques to protect SRDs impose significant area and power overheads. Additionally, they suffer from susceptibility of configuration bits to multiple bit upsets (MBUs). In this paper, we present a highly available fault-tolerant architecture to protect SRD-based designs against MBUs in both configuration and user bits. In the proposed architecture, the entire design is duplicated with respect to the relative locations of logic blocks within the SRD and... 

The dynamic nature of today’s manufacturing industry, which is caused by the intense global competition and constant technological advancements, requires systems that are highly adaptive and responsive to demand fluctuations. Reconfigurable manufacturing systems (RMS) enable such responsiveness through their main characteristics. This paper addresses the problem of RMS configuration design, where the demand of a single product varies throughout its production life cycle, and the system configuration must change accordingly to satisfy the required demand with minimum cost. A two-phased method is developed to handle the primary system configuration design and the necessary system... 

In this brief, we present a fine-grained dark silicon architecture to facilitate further integration of transistors in static random access memory-based reconfigurable devices. In the proposed architecture, we present a technique to power off inactive configuration cells in nonutilized or underutilized logic blocks. We also propose a routing circuitry capable of turning off the configuration cells of connection blocks (CBs) and switch boxes (SBs) in the routing fabric. Experimental results carried out on the Microelectronics Center of North Carolina benchmark show that power consumption in configuration cells of lookup tables, CBs, and SBs can, on average, be reduced by 27%, 75%, and 4%,... 

Networks-on-Chip (NoCs) play a crucial role in the performance of Chip Multi-Processors (CMPs). Routers are one of the main components determining the efficiency of NoCs. As various applications have different communication characteristics and hence, buffering requirements, it is difficult to make proper decisions in this regard in the design time. In this paper, we propose a traffic-aware reconfigurable router which can adapt its buffers structure to the changes in the traffic of the network. Our proposed router manages to achieve up to 18.8% and 44.4% improvements in terms of postponing saturation rate under synthetic traffic patterns, and average packet latency for PARSEC applications,...