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    Toward A Safe, Assured, and Dynamic Communication Protocol Stack

    , Ph.D. Dissertation Sharif University of Technology Niamanesh, Mahdi (Author) ; Jalili, Rasool (Supervisor)

    Fault-tolerant five-leg converter topology with FPGA-Based reconfigurable control

    , Article IEEE Transactions on Industrial Electronics ; Volume 60, Issue 6 , 2013 , Pages 2284-2294 ; 02780046 (ISSN) Shahbazi, M ; Poure, P ; Saadate, S ; Zolghadri, M. R ; Sharif University of Technology
    Fast fault detection and reconfiguration of power converters is necessary in electrical drives to prevent further damage and to make the continuity of service possible. On the other hand, component minimized converters may provide the benefits of higher reliability and less volume and cost. In this paper, a new fault-tolerant converter topology is studied. This converter has five legs before the fault occurrence, and after fault detection the converter continues to function with four legs. A very fast fault detection and reconfiguration scheme is presented and studied. Simulations and experimental tests are performed to evaluate the structure requirements, the digital reconfigurable... 

    FPGA-based reconfigurable control for fault-tolerant back-to-back converter without redundancy

    , Article IEEE Transactions on Industrial Electronics ; Volume 60, Issue 8 , May , 2013 , Pages 3360-3371 ; 02780046 (ISSN) Shahbazi, M ; Poure, P ; Saadate, S ; Zolghadri, M. R ; Sharif University of Technology
    In this paper, an FPGA-based fault-tolerant back-to-back converter without redundancy is studied. Before fault occurrence, the fault-tolerant converter operates like a conventional back-to-back six-leg converter, and after the fault, it becomes a five-leg converter. Design, implementation, and experimental verification of an FPGA-based reconfigurable control strategy for this converter are discussed. This reconfigurable control strategy allows the continuous operation of the converter with minimum affection from a fault in one of the semiconductor switches. A very fast detection scheme is used to detect and locate the fault. Implementation of the fault detection and of the fully digital... 

    PEAF: A power-efficient architecture for SRAM-based fpgas using reconfigurable hard logic design in dark silicon era

    , Article IEEE Transactions on Computers ; Volume 66, Issue 6 , 2017 , Pages 982-995 ; 00189340 (ISSN) Ebrahimi, Z ; Khaleghi, B ; Asadi, H ; Sharif University of Technology
    IEEE Computer Society  2017
    Significant increase of static power in nano-CMOS era and, subsequently, the end of Dennard scaling has put a Power Wall to further integration of CMOS technology in Field-Programmable Gate Arrays (FPGAs). An efficient solution to cope with this obstacle is power gating inactive fractions of a single die, resulting in Dark Silicon. Previous studies employing power gating on SRAM-based FPGAs have primarily focused on using large-input Look-up Tables (LUTs). The architectures proposed in such studies inherently suffer from poor logic utilization which limits the benefits of power gating techniques. This paper proposes a Power-Efficient Architecture for FPGAs (PEAF) based on combination of...