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Evaluation of Fault Tolerance for SRAM-Based FPGAs by Fault Injection into Configuration Bits
, M.Sc. Thesis Sharif University of Technology ; Miremadi, Ghasem (Supervisor)
Abstract
Reconfiguration, short development time and low cost have made Field Programmable Gate Arrays (FPGAs) an appealing option for digital circuit designers. Meanwhile, the occurrence of Single Event Upset (SEU) in configuration memory of SRAM-based FPGAs can change the implemented design inside the FPGA chip. Assessing reliability of FPGA-based designs against pernicious effects of SEU has long been a challenge. Several approaches can be used to evaluate the reliability of a given design. One important approach is injecting fault into the configuration memory of a device.The existing fault injection frameworks are specific in the property e.g. providing speed only, neglecting other properties of...
Emerging non-volatile memory technologies for future low power reconfigurable systems
, Article 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC ; 26-28 May , 2014 , pp. 1-2 ; 9781479958108 ; Asadi, H ; Tahoori, M. B ; Sharif University of Technology
Abstract
Non-volatile memory (NVM) technologies are promising alternatives to traditional CMOS memory technologies. While NVMs were primarily studied to be used in the memory hierarchy, they can also provide benefits in reconfigurable systems such as Field-Programmable Gate Arrays (FPGAs). In this paper, we investigate the applicability of different NVM technologies for the configuration bits of FPGAs and propose a power-efficient reconfigurable architecture based on Phase Change Memory (PCM). Quantitative analysis for various FPGA architectures using different memory technologies shows the benefits of the proposed scheme
Synthesis of a Group of Mechanisms with Dual Function Depending on the Input Velocities
, M.Sc. Thesis Sharif University of Technology ; Fallah Rajabzadeh, Famida (Supervisor) ; Zohoor, Hassan (Supervisor)
Abstract
Compliant mechanisms are generally used in quasi-static condition and therefore system dynamics do not have a significant effect on their performance; But if the inertia of the links is high, the dynamics of the mechanism will affect its performance altogether. By cleverly designing the mechanism, these effects can be used to create new movement patterns. In this research, a family of compliant mechanisms is introduced whose movement patterns are a function of input speeds. This means that at low speeds, the flexibility of the mechanism does not have a significant effect on its performance, but when the speed exceeds a certain limit, this flexibility changes the configuration of the...
Toward operational resilience of smart energy networks in complex infrastructures
, Article Advances in Intelligent Systems and Computing ; Volume 1123 , 2020 , Pages 203-228 ; Jalilian, A ; Safdarian, A ; Moeini Aghtaie, M ; Lehtonen, M ; Sharif University of Technology
Springer
2020
Abstract
Smart energy systems can mitigate electric interruption costs provoked by manifold disruptive events via making efforts toward proper pre-disturbance preparation and optimal post-disturbance restoration. In this context, effective contingency management in power distribution networks calls for contemplating disparate parameters from interconnected electric and transportation systems. This chapter, while considering transportation issues in power networks’ field operations, presents a navigation system for pre-positioning resources such as field crews and reconfiguring the network to acquire a more robust configuration in advance of the imminent catastrophe. Also, after the occurrence of the...
Application-aware topology reconfiguration for on-chip networks
, Article IEEE Transactions on Very Large Scale Integration (VLSI) Systems ; Volume 19, Issue 11 , 2011 , Pages 2010-2022 ; 10638210 (ISSN) ; Tavakkol, A ; Sarbazi Azad, H ; Sharif University of Technology
Abstract
In this paper, we present a reconfigurable architecture for networks-on-chip (NoC) on which arbitrary application-specific topologies can be implemented. When a new application starts, the proposed NoC tailors its topology to the application traffic pattern by changing the inter-router connections to some predefined configuration corresponding to the application. It addresses one of the main drawbacks of the existing application-specific NoC optimization methods, i.e., optimization of NoCs based on the traffic pattern of a single application. Supporting multiple applications is a critical feature of an NoC when several different applications are integrated into a single modern and complex...