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A ZVS-resonant bifilar drive circuit for SRM with a reduction in stress voltage of switches
, Article International Aegean Conference on Electrical Machines and Power Electronics, ACEMP 2011 and Electromotion 2011 Joint Conference, Istanbul ; 2013 , Pages 125-128 ; 9781467350037 (ISBN) ; Najmi, V ; Ebrahimi, S ; Oraee, H ; Sharif University of Technology
2013
Abstract
Switched Reluctance Motors (SRMs) are widely used in high-speed and low voltage applications because of their attractive features such as robustness and simplicity. No winding on the rotor of this type of motors allows reaching high speed which is desired for many applications. Drive circuits of SRMs also play an important role in their performance and operation. In this paper, a new bifilar drive circuit for this type of motors has been proposed. This novel configuration has been tested and investigated by PSIM software. Results show that the new bifilar drive circuit highly reduces the voltage stresses on semiconductor switches, and also considerably reduces the switching losses which are...
A reduced switch cascaded transformer multi level inverter
, Article 2015 IEEE 15th International Conference on Environment and Electrical Engineering, EEEIC 2015 - Conference Proceedings, 10 June 2015 through 13 June 2015 ; 2015 , Pages 1013-1018 ; 9781479979936 (ISBN) ; Khodabandeh, M ; Zolghadri, M ; Rodriguez, J ; Oraee, H ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2015
Abstract
In this paper, a novel reduced switch cascaded transformer multilevel inverter is proposed. In this structure, a new structure is replaced with conventional H-bridge inverter. It consists of four high frequency switches, two line frequency switches, and two transformers which can be assembled in one core with a specific winding connection. This topology can produce 5 or 7 voltage levels depending on transformers turns ratio. The simplicity and modularity are its advantages compared to the existing structures. Beside these advantages, due to its similarity with H-Bridge converter, it is possible to use a modified technique based on conventional phase shift pulse width modulation to generate...
Implementation and hardware in the loop verification of five-leg converter control system on a FPGA
, Article IECON Proceedings (Industrial Electronics Conference), 7 November 2011 through 10 November 2011, Melbourne, VIC ; 2011 , Pages 4015-4020 ; 9781612849720 (ISBN) ; Zolghadri, M. R ; Poure, P ; Saadate, S ; Sharif University of Technology
2011
Abstract
FPGAs are interesting choices for control of power electronics converters and electrical drives. In this paper, implementation of the control method of a reduced switch- count five-leg converter is carried out. Two PWM methods are studied. For verification of the implemented controller in a practical manner, without risking the damaging of the real system, "FPGA in the loop" experiments are performed. It is shown that using the proposed methodology, FPGA implementation and verification is fast and effective. The provided results show the high performance of the implemented controller on the FPGA, therefore the feasibility and suitability of the FPGA for this application is approved