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Design of low power comparator-reduced hybrid ADC
, Article Microelectronics Journal ; Volume 79 , 2018 , Pages 79-90 ; 00262692 (ISSN) ; Hajsadeghi, K ; Khorami, A ; Sharif University of Technology
Elsevier Ltd
2018
Abstract
This paper presents a new low-power comparator-reduced hybrid ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce the offset and kickback noise effect of conventional dynamic comparators, a new low-kickback noise comparator with a high pre-amplifier gain is presented. Two 4bit and 8bit ADCs are designed and simulated in 0.18 μm CMOS technology with 1.8 v supply voltage. INL and DNL of 4bit ADC are less than 0.4LSB and 0.5LSB, respectively, while 8bit ADC obtains DNL and INL of 0.83LSB and 1.3LSB, respectively. With ENOB of 3.6bit and 7.2bit for 4bit and 8bit ADCs, the 4bit ADC consumes only 1.7 mW at the sampling rate of 400 Ms/s...
A low-power comparator-reduced flash ADC using dynamic comparators
, Article 24th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2017, 5 December 2017 through 8 December 2017 ; Volume 2018-January , 2018 , Pages 5-8 ; 9781538619117 (ISBN) ; Hajsadeghi, K ; Sharif University of Technology
Institute of Electrical and Electronics Engineers Inc
2018
Abstract
This paper presents a new low-power reduced comparator flash ADC. The proposed ADC uses dynamic comparators to perform a high-speed low-power conversion. In order to reduce offset and kick-back noise effect of conventional dynamic comparators, a new comparator with a higher pre-amplifier gain along with the mathematical analysis is presented. The proposed 4bit ADC is simulated in 0.18um with 1.8-υ supply voltage. SNDR and SFDR of the ADC are 23dB and 26.5dB, respectively. The ADC consumes only 0.95mw at the sampling rate of 400MS/s. © 2017 IEEE